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1. 发明授权

US08906727B2 Heteroepitaxial growth using ion implantation 有权
标题翻译：使用离子注入的异质外延生长
公开(公告)号：US08906727B2
公开(公告)日：2014-12-09
申请号：US13517535
申请日：2012-06-13
申请人： Morgan D. Evans , Chi-Chun Chen , Cheng-Huang Kuo
发明人： Morgan D. Evans , Chi-Chun Chen , Cheng-Huang Kuo
IPC分类号： H01L21/00 , C30B23/02 , C30B29/40 , C30B25/18
CPC分类号： C30B23/025 , C30B25/186 , C30B29/403
摘要： In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.
摘要翻译：在一个实施例中，生长异质外延层的方法包括提供包含具有侧壁的图案化特征的图案化衬底。该方法还包括在曝光中将离子引向侧壁，其中形成改变的侧壁区域，并且在与图案化特征的其它表面相比有效地优先促进侧壁上的外延生长的一组沉积条件下沉积异质外延层。

2. 发明申请

US20130020580A1 HETEROEPITAXIAL GROWTH USING ION IMPLANTATION 有权
标题翻译：使用离子植入进行异位生长
公开(公告)号：US20130020580A1
公开(公告)日：2013-01-24
申请号：US13517535
申请日：2012-06-13
申请人： Morgan D. Evans , Chi-Chun Chen , Cheng-Huang Kuo
发明人： Morgan D. Evans , Chi-Chun Chen , Cheng-Huang Kuo
IPC分类号： H01L21/20 , H01L33/32
CPC分类号： C30B23/025 , C30B25/186 , C30B29/403
摘要： In one embodiment, a method of growing a heteroepitaxial layer comprises providing a patterned substrate containing patterned features having sidewalls. The method also includes directing ions toward the sidewalls in an exposure, wherein altered sidewall regions are formed, and depositing the heteroepitaxial layer under a set of deposition conditions effective to preferentially promote epitaxial growth on the sidewalls in comparison to other surfaces of the patterned features.
摘要翻译：在一个实施例中，生长异质外延层的方法包括提供包含具有侧壁的图案化特征的图案化衬底。该方法还包括在曝光中将离子引向侧壁，其中形成改变的侧壁区域，并且在与图案化特征的其它表面相比有效地优先促进侧壁上的外延生长的一组沉积条件下沉积异质外延层。

3. 发明授权

US08815720B2 Method of etching a workpiece 有权
标题翻译：蚀刻工件的方法
公开(公告)号：US08815720B2
公开(公告)日：2014-08-26
申请号：US13440678
申请日：2012-04-05
申请人： Ludovic Godet , Morgan D. Evans , Chi-Chun Chen
发明人： Ludovic Godet , Morgan D. Evans , Chi-Chun Chen
IPC分类号： H01L21/302 , H01L21/322
CPC分类号： H01L21/30621 , H01L21/30612 , H01L33/007 , H01L33/0095 , H01L43/12
摘要： A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.
摘要翻译：将工件植入第一深度以形成第一非晶化区域。然后将该非晶化区域蚀刻到第一深度。在蚀刻之后，将工件植入第二深度以在第一非晶化区域的位置下方形成第二非晶化区域。然后将第二非晶区域蚀刻到第二深度。可以重复植入和蚀刻步骤，直到形成结构为期望的深度。工件可以是例如化合物半导体，例如GaN，磁性材料，硅或其它材料。

4. 发明申请

US20120276658A1 METHOD OF ETCHING A WORKPIECE 有权
标题翻译：蚀刻工作的方法
公开(公告)号：US20120276658A1
公开(公告)日：2012-11-01
申请号：US13440678
申请日：2012-04-05
申请人： Ludovic Godet , Morgan D. Evans , Chi-Chun Chen
发明人： Ludovic Godet , Morgan D. Evans , Chi-Chun Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/30621 , H01L21/30612 , H01L33/007 , H01L33/0095 , H01L43/12
摘要： A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.
摘要翻译：将工件植入第一深度以形成第一非晶化区域。然后将该非晶化区域蚀刻到第一深度。在蚀刻之后，将工件植入第二深度以在第一非晶化区域的位置下方形成第二非晶化区域。然后将第二非晶区域蚀刻到第二深度。可以重复植入和蚀刻步骤，直到形成结构为期望的深度。工件可以是例如化合物半导体，例如GaN，磁性材料，硅或其它材料。

5. 发明申请

US20130181186A1 INTEGRATION OF CURRENT BLOCKING LAYER AND n-GaN CONTACT DOPING BY IMPLANTATION 失效
标题翻译：通过植入来集成电流阻挡层和n-GaN接触式掺杂
公开(公告)号：US20130181186A1
公开(公告)日：2013-07-18
申请号：US13351039
申请日：2012-01-16
申请人： Tao Jiang , Chi-Chun Chen
发明人： Tao Jiang , Chi-Chun Chen
IPC分类号： H01L33/06
CPC分类号： H01L33/0095 , H01L33/14 , H01L33/145 , H01L33/32
摘要： An improved method of fabricating a semiconductor light emitting diode (LED) is disclosed. The current blocking layer and the contact area for the n-type layer are implanted at the same time. In some embodiments, a dopant, which may be an n-type dopant, is implanted into a portion of the p-type layer to cause that portion to become either u-type or n-type. Simultaneously, the same dopant is implanted into at least a portion of the exposed n-type layer to increase its conductivity. After this implant, the dopant in both portions of the LED may be activated through the use of a single anneal cycle.
摘要翻译：公开了一种制造半导体发光二极管（LED）的改进方法。同时植入电流阻挡层和n型层的接触面积。在一些实施例中，可以将n型掺杂剂掺杂到p型层的一部分中以使该部分成为u型或n型。同时，将相同的掺杂剂注入到暴露的n型层的至少一部分中以增加其导电性。在该植入之后，LED的两个部分中的掺杂剂可以通过使用单个退火循环而被激活。

6. 发明授权

US08222132B2 Fabricating high-K/metal gate devices in a gate last process 有权
标题翻译：在最后一道工序中制造高K /金属栅极器件
公开(公告)号：US08222132B2
公开(公告)日：2012-07-17
申请号：US12567227
申请日：2009-09-25
申请人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
发明人： Da-Yuan Lee , Jian-Hao Chen , Chi-Chun Chen , Matt Yeh , Hsing-Jui Lee
IPC分类号： H01L21/3205
CPC分类号： H01L21/823814 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L29/7848
摘要： The present disclosure provides a method that includes forming first and second gate structures over first and second regions, respectively, removing a first dummy gate and first dummy dielectric from the first gate structure thereby forming a first trench and removing a second dummy gate and second dummy dielectric from the second gate structure thereby forming a second trench, forming a gate layer to partially fill the first and second trenches, forming a material layer to fill the remainder of the first and second trenches, removing a portion of the material layer such that a remaining portion of the material layer protects a first portion of the gate layer located at a bottom portion of the first and second trenches, removing a second portion of the gate layer, removing the remaining portion of the material layer from the first and second trenches.
摘要翻译：本公开提供了一种方法，其包括分别在第一和第二区域上形成第一和第二栅极结构，从第一栅极结构去除第一伪栅极和第一虚设电介质，从而形成第一沟槽并且去除第二虚拟栅极和第二虚拟栅极从第二栅极结构的电介质，从而形成第二沟槽，形成栅极层以部分地填充第一和第二沟槽，形成材料层以填充第一和第二沟槽的其余部分，去除材料层的一部分，使得材料层的剩余部分保护位于第一和第二沟槽的底部的栅极层的第一部分，去除栅极层的第二部分，从第一和第二沟槽去除材料层的剩余部分。

7. 发明申请

US20110316079A1 Shallow Junction Formation and High Dopant Activation Rate of MOS Devices 有权
标题翻译： MOS器件的浅结点形成和高掺杂激活速率
公开(公告)号：US20110316079A1
公开(公告)日：2011-12-29
申请号：US13228182
申请日：2011-09-08
申请人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
发明人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/665 , H01L29/6659
摘要： A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.
摘要翻译：半导体结构包括半导体衬底中的栅极堆叠和半导体衬底中的轻掺杂源极/漏极（LDD）区域。 LDD区域与栅堆叠下方的区域相邻。 LDD区域包含碳和n型杂质，n型杂质包括磷四聚体。

8. 发明授权

US08039375B2 Shallow junction formation and high dopant activation rate of MOS devices 有权
标题翻译：浅结点形成和MOS器件的高掺杂剂激活率
公开(公告)号：US08039375B2
公开(公告)日：2011-10-18
申请号：US11804927
申请日：2007-05-21
申请人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
发明人： Chun-Feng Nieh , Keh-Chiang Ku , Nai-Han Cheng , Chi-Chun Chen , Li-Te S. Lin
IPC分类号： H01L21/22 , H01L21/38 , H01L35/22
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/665 , H01L29/6659
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅叠层; 将碳注入到半导体衬底中; 以及将n型杂质注入所述半导体衬底中以形成轻掺杂的源极/漏极（LDD）区域，其中所述n型杂质包含多于一个的磷原子。 n型杂质可以包括磷二聚体或磷酸四聚体。

9. 发明申请

US20110244616A1 VERTICAL STRUCTURE LED CURRENT SPREADING BY IMPLANTED REGIONS 失效
标题翻译：嵌入式区域的垂直结构LED电流扩展
公开(公告)号：US20110244616A1
公开(公告)日：2011-10-06
申请号：US13074137
申请日：2011-03-29
申请人： San Yu , Chi-Chun Chen
发明人： San Yu , Chi-Chun Chen
IPC分类号： H01L33/26
CPC分类号： H01L33/145 , H01L33/0079
摘要： An improved method of fabricating a vertical semiconductor LED is disclosed. Ions are implanted into the LED to create non-conductive regions, which facilitates current spreading in the device. In some embodiments, the non-conductive regions are located in the p-type layer. In other embodiments, the non-conductive layer may be in the multi-quantum well or n-type layer.
摘要翻译：公开了一种制造垂直半导体LED的改进方法。将离子注入到LED中以产生非导电区域，这有助于电流在器件中的扩散。在一些实施例中，非导电区域位于p型层中。在其它实施例中，非导电层可以在多量子阱或n型层中。

10. 发明申请

US20110117734A1 Method of Fabricating High-K Poly Gate Device 审中-公开
标题翻译：制造高K多栅极器件的方法
公开(公告)号：US20110117734A1
公开(公告)日：2011-05-19
申请号：US13014548
申请日：2011-01-26
申请人： Da-Yuan Lee , Chien-Hao Huang , Chi-Chun Chen , Kang-Cheng Lin
发明人： Da-Yuan Lee , Chien-Hao Huang , Chi-Chun Chen , Kang-Cheng Lin
IPC分类号： H01L21/28
CPC分类号： H01L29/513 , H01L21/823828 , H01L29/4966 , H01L29/518
摘要： The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.
摘要翻译：本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

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