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    • 6. 发明申请
    • MALICIOUS CODE DETECTION
    • 恶意代码检测
    • US20120023578A1
    • 2012-01-26
    • US13259307
    • 2009-10-31
    • David A. Warren
    • David A. Warren
    • G06F21/00
    • H04L63/1416G06F21/564G06F21/567
    • A device includes a pipeline and a detector that are both implemented at least in hardware. Data is moved through the pipeline to perform processing of the data unrelated to detection of malicious code. The detector detects the malicious code within the data as the data is moved through the pipeline, in parallel with the processing of the data as the data is moved through the pipeline. The detector detects the malicious code within the data as the data is moved through the pipeline without delaying movement of the data into, through, and out of the pipeline.
    • 一种设备包括至少以硬件实现的流水线和检测器。 通过流水线移动数据,对与恶意代码的检测无关的数据进行处理。 当数据通过管道移动时,检测器与数据的处理并行地检测数据中的恶意代码,因为数据被移动通过流水线。 当数据通过流水线移动时,检测器检测数据内的恶意代码,而不会延迟数据进入管道中,并通过管道移出。
    • 8. 发明授权
    • Malicious code detection
    • 恶意代码检测
    • US09032517B2
    • 2015-05-12
    • US13259307
    • 2009-10-31
    • David A. Warren
    • David A. Warren
    • G06F11/00H04L29/06G06F21/56
    • H04L63/1416G06F21/564G06F21/567
    • A device includes a pipeline and a detector that are both implemented at least in hardware. Data is moved through the pipeline to perform processing of the data unrelated to detection of malicious code. The detector detects the malicious code within the data as the data is moved through the pipeline, in parallel with the processing of the data as the data is moved through the pipeline. The detector detects the malicious code within the data as the data is moved through the pipeline without delaying movement of the data into, through, and out of the pipeline.
    • 一种设备包括至少以硬件实现的流水线和检测器。 通过流水线移动数据,对与恶意代码的检测无关的数据进行处理。 当数据通过管道移动时,检测器与数据的处理并行地检测数据中的恶意代码,因为数据被移动通过流水线。 当数据通过流水线移动时,检测器检测数据内的恶意代码,而不会延迟数据进入管道中,并通过管道移出。
    • 9. 发明申请
    • Performance of first and second macros while data is moving through hardware pipeline
    • 当数据通过硬件管道移动时,第一个和第二个宏的性能
    • US20110107061A1
    • 2011-05-05
    • US12610208
    • 2009-10-30
    • David A. Warren
    • David A. Warren
    • G06F15/76G06F9/02G06F9/30
    • H04L61/2514
    • A hardware pipeline has a number of rows including a first row, a last row, and an intermediate row between the first row and the last row. Each row stores a number of bytes of data as the data moves through the pipeline on a row-by-row basis from the first row towards the last row. A mechanism performs a first macro on the data beginning at the first row. The mechanism performs a second macro different than the first macro on the data beginning at the intermediate row where the first macro has been completely performed when the data has reached the intermediate row. The first and second macros each include a number of modifications of the data as the data moves through the pipeline to effect a complete transformation of the data. The complete transformation of the first macro is different than the complete transformation of the second data.
    • 硬件流水线具有包括第一行,最后一行和第一行和最后一行之间的中间行的多行。 当数据从第一行朝向最后一行逐行地移动时,每行存储数据字节数。 机制在第一行开始的数据上执行第一个宏。 当数据到达中间行时,该机制执行与第一个宏不同的第二个宏,该数据从中间行开始,其中第一个宏已经被完全执行。 当数据移动通过流水线以实现数据的完全转换时,第一和第二宏每个包括数据的许多修改。 第一个宏的完全转换与第二个数据的完全转换不同。