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1. 发明授权

US08450792B2 Structure and fabrication method of tunnel field effect transistor with increased drive current and reduced gate induced drain leakage (GIDL) 有权
标题翻译：隧道场效应晶体管的结构和制造方法具有增加的驱动电流和降低的栅极引起的漏极泄漏（GIDL）
公开(公告)号：US08450792B2
公开(公告)日：2013-05-28
申请号：US13082867
申请日：2011-04-08
申请人： Mohit Bajaj , Kota V. R. M. Murali , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Kota V. R. M. Murali , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H01L29/792
CPC分类号： H01L29/7391 , H01L29/045 , H01L29/0657 , H01L29/66356
摘要： Gate induced drain leakage in a tunnel field effect transistor is reduced while drive current is increased by orienting adjacent semiconductor bodies, based on their respective crystal orientations or axes, to optimize band-to-band tunneling at junctions. Maximizing band-to-band tunneling at a source-channel junction increases drive current, while minimizing band-to-band tunneling at a channel-drain junction decreases GIDL. GIDL can be reduced by an order of magnitude in an embodiment. Power consumption for a given frequency can also be reduced by an order of magnitude.
摘要翻译：通过基于它们各自的晶体取向或轴定向相邻的半导体本体来增加隧道场效应晶体管中的栅极感应漏极泄漏，同时通过使相邻的半导体本体取向来提高驱动电流，以优化在结处的带 - 带隧穿。在源极 - 沟道结上最大化带 - 带隧穿可增加驱动电流，同时最小化通道 - 漏极结上的带 - 带隧穿可以减小GIDL。在实施例中，GIDL可以减少一个数量级。给定频率的功耗也可以减少一个数量级。

2. 发明授权

US09105498B2 Gate strain induced work function engineering 有权
公开(公告)号：US09105498B2
公开(公告)日：2015-08-11
申请号：US13409630
申请日：2012-03-01
申请人： Mohit Bajaj , Kota V. R. M. Murali , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Kota V. R. M. Murali , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H01L21/8238 , H01L27/092 , H01L21/8234 , H01L21/84 , H01L27/12 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/823412 , H01L21/82345 , H01L21/823821 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L29/7845
摘要： A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.

3. 发明申请

US20130314825A1 SILICON CONTROLLED RECTIFIER (SCR) CLAMP INCLUDING METAL INSULATOR TRANSITION (MIT) RESISTOR 有权
标题翻译：硅控制整流器（SCR）钳位，包括金属绝缘子转换（MIT）电阻
公开(公告)号：US20130314825A1
公开(公告)日：2013-11-28
申请号：US13479328
申请日：2012-05-24
申请人： Mohit Bajaj , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H02H9/04 , G06F17/50
CPC分类号： H02H9/046
摘要： Aspects of the invention provide for an electrostatic discharge (ESD) clamp. In one embodiment, the ESD clamp includes: a silicon controlled rectifier (SCR); and a trigger circuit for providing a tunable trigger voltage to turn on the SCR, the trigger circuit including a metal-insulator transition (MIT) material. The trigger circuit includes an MIT resistor that includes a width and a length that tunes the trigger voltage to a desired voltage.
摘要翻译：本发明的方面提供静电放电（ESD）夹具。在一个实施例中，ESD钳位包括：可控硅整流器（SCR）; 以及用于提供可调谐触发电压以接通SCR的触发电路，所述触发电路包括金属 - 绝缘体转变（MIT）材料。触发电路包括MIT电阻器，其包括将触发电压调谐到期望电压的宽度和长度。

4. 发明授权

US08929039B2 Silicon controlled rectifier (SCR) clamp including metal insulator transition (MIT) resistor 有权
标题翻译：可控硅整流器（SCR）钳位包括金属绝缘子转换（MIT）电阻
公开(公告)号：US08929039B2
公开(公告)日：2015-01-06
申请号：US13479328
申请日：2012-05-24
申请人： Mohit Bajaj , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H01L49/00
CPC分类号： H02H9/046
摘要： Aspects of the invention provide for an electrostatic discharge (ESD) clamp. In one embodiment, the ESD clamp includes: a silicon controlled rectifier (SCR); and a trigger circuit for providing a tunable trigger voltage to turn on the SCR, the trigger circuit including a metal-insulator transition (MIT) material. The trigger circuit includes an MIT resistor that includes a width and a length that tunes the trigger voltage to a desired voltage.
摘要翻译：本发明的方面提供静电放电（ESD）夹具。在一个实施例中，ESD钳位包括：可控硅整流器（SCR）; 以及用于提供可调谐触发电压以接通SCR的触发电路，所述触发电路包括金属 - 绝缘体转变（MIT）材料。触发电路包括MIT电阻器，其包括将触发电压调谐到期望电压的宽度和长度。

5. 发明申请

US20130228872A1 GATE STRAIN INDUCED WORK FUNCTION ENGINEERING 有权
公开(公告)号：US20130228872A1
公开(公告)日：2013-09-05
申请号：US13409630
申请日：2012-03-01
申请人： Mohit Bajaj , Kota V.R.M. Murali , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Kota V.R.M. Murali , Rahul Nayak , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H01L27/092 , H01L21/28
CPC分类号： H01L27/0922 , H01L21/823412 , H01L21/82345 , H01L21/823821 , H01L21/845 , H01L27/092 , H01L27/0924 , H01L27/1211 , H01L29/7845
摘要： A stack of a gate dielectric layer and a workfunction material layer are deposited over a plurality of semiconductor material portions, which can be a plurality of semiconductor fins or a plurality of active regions in a semiconductor substrate. A first gate conductor material applying a first stress is formed on a first portion of the workfunction material layer located on a first semiconductor material portion, and a second gate conductor material applying a second stress is formed on a second portion of the workfunction material layer located on a second semiconductor material portion. The first and second stresses are different in at least one of polarity and magnitude, thereby inducing different strains in the first and second portions of the workfunction material layer. The different strains cause the workfunction shift differently in the first and second portions of the workfunction material layer, thereby providing devices having multiple different workfunctions.

6. 发明申请

US20120256248A1 STRUCTURE AND FABRICATION METHOD OF TUNNEL FIELD EFFECT TRANSISTOR WITH INCREASED DRIVE CURRENT AND REDUCED GATE INDUCED DRAIN LEAKAGE (GIDL) 有权
标题翻译：隧道场效应晶体管的结构和制造方法具有增加的驱动电流和降低的栅极诱发的漏极泄漏（GIDL）
公开(公告)号：US20120256248A1
公开(公告)日：2012-10-11
申请号：US13082867
申请日：2011-04-08
申请人： Mohit Bajaj , Kota V.R.M. Murali , Edward J. Nowak , Rajan K. Pandey
发明人： Mohit Bajaj , Kota V.R.M. Murali , Edward J. Nowak , Rajan K. Pandey
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/7391 , H01L29/045 , H01L29/0657 , H01L29/66356
摘要： Gate induced drain leakage in a tunnel field effect transistor is reduced while drive current is increased by orienting adjacent semiconductor bodies, based on their respective crystal orientations or axes, to optimize band-to-band tunneling at junctions. Maximizing band-to-band tunneling at a source-channel junction increases drive current, while minimizing band-to-band tunneling at a channel-drain junction decreases GIDL. GIDL can be reduced by an order of magnitude in an embodiment. Power consumption for a given frequency can also be reduced by an order of magnitude.
摘要翻译：通过基于它们各自的晶体取向或轴定向相邻的半导体本体来增加隧道场效应晶体管中的栅极感应漏极泄漏，同时通过使相邻的半导体本体取向来提高驱动电流，以优化在结处的带 - 带隧穿。在源极 - 沟道结上最大化带 - 带隧穿可增加驱动电流，同时最小化通道 - 漏极结上的带 - 带隧穿可以减小GIDL。在实施例中，GIDL可以减少一个数量级。给定频率的功耗也可以减少一个数量级。

7. 发明授权

US09368410B2 Semiconductor devices having tensile and/or compressive stress and methods of manufacturing 有权
标题翻译：具有拉伸和/或压缩应力的半导体器件和制造方法
公开(公告)号：US09368410B2
公开(公告)日：2016-06-14
申请号：US12033280
申请日：2008-02-19
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Edmund J. Sprogis
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/76205 , H01L21/823878 , H01L29/7846
摘要： A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
摘要翻译：公开了一种半导体器件和制造方法，其具有施加到其上的拉伸和/或压缩应变。该方法包括在材料中形成至少一个沟槽; 以及通过氧化工艺填充所述至少一个沟槽，从而在器件的通道中形成应变集中。该结构包括分别在第一通道上具有沟道和第一氧化沟槽的栅极结构。第一氧化沟槽在通道中产生应变分量以增加器件性能。

8. 发明授权

US08866226B2 SOI radio frequency switch with enhanced electrical isolation 有权
标题翻译： SOI射频开关具有增强的电气隔离
公开(公告)号：US08866226B2
公开(公告)日：2014-10-21
申请号：US13345871
申请日：2012-01-09
申请人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
发明人： Alan B. Botula , Alvin J. Joseph , Edward J. Nowak , Yun Shi , James A. Slinkman
IPC分类号： H01L27/12 , H01L21/84 , H01L21/762
CPC分类号： H01L21/84 , H01L21/76264 , H01L27/1203
摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.
摘要翻译：至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

9. 发明授权

US08673683B2 Graphene field effect transistor 有权
标题翻译：石墨烯场效应晶体管
公开(公告)号：US08673683B2
公开(公告)日：2014-03-18
申请号：US13492131
申请日：2012-06-08
申请人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
发明人： James W. Adkisson , Thomas J. Dunbar , Jeffrey P. Gambino , Molly J. Leitch , Edward J. Nowak
IPC分类号： H01L51/40 , H01L21/8232 , H01L21/336
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/186 , H01L27/1222 , H01L29/41733 , H01L29/42384 , H01L29/66045 , H01L29/66742 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： Manufacturing a semiconductor structure including: forming a seed material on an insulator layer; forming a graphene field effect transistor (FET) on the seed material; and forming an air gap under the graphene FET by removing the seed material.
摘要翻译：制造半导体结构，包括：在绝缘体层上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并通过除去种子材料在石墨烯FET下方形成气隙。

10. 发明授权

US08617412B2 Nano-filter and method of forming same, and method of filtration 失效
标题翻译：纳米过滤器及其形成方法及过滤方法
公开(公告)号：US08617412B2
公开(公告)日：2013-12-31
申请号：US12966370
申请日：2010-12-13
申请人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
发明人： Brent A. Anderson , Andres Bryant , Edward J. Nowak , Jeffrey W. Sleight
IPC分类号： C23F3/00 , B01D29/46 , H01L21/02
CPC分类号： B01D39/2082 , B01D2239/025 , B01D2239/0613 , B01D2239/10 , B01D2239/1233 , B82Y30/00
摘要： The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.
摘要翻译：本公开一般涉及纳米过滤器及其形成方法，以及过滤方法。纳米过滤器包括基底和位于入口和出口之间的至少一个纳米线结构。纳米线结构可以包括多个垂直堆叠的水平纳米线。

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