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1. 发明授权

US5901065A Apparatus and method for automatically placing ties and connection elements within an integrated circuit 失效
标题翻译：在集成电路内自动放置连接元件和连接元件的装置和方法
公开(公告)号：US5901065A
公开(公告)日：1999-05-04
申请号：US597768
申请日：1996-02-07
申请人： Mohan Guruswamy , Daniel W. Dulitz , Robert Maziasz
发明人： Mohan Guruswamy , Daniel W. Dulitz , Robert Maziasz
IPC分类号： G06F17/50 , G06Q10/04 , H01L27/02 , H01L27/092 , G06F17/00
CPC分类号： G06F17/5068 , G06Q10/043 , H01L27/0203 , H01L27/0921
摘要： Methods (100, 200, 250) and data processing system (300) for automatically placing ties (136, 138, 146, 148) and connection elements within an integrated circuit (120). Integrated circuit dimensions (102), element locations and element dimensions (104), and tie placement rules (106) are received for a particular integrated circuit (120). The quantities are then processed to place ties within the integrated circuit (108). Tie placement rules include tie spacings (164, 166), well edge spacings (162), and diffusion spacings (168) to prevent SCR latch up and gate threshold voltage drift. Tie placement methods (100, 200) automatically place ties within the integrated circuit (120) to comply with tie spacing rules and also consider estimated compactions so that tie numbers are minimized. Associated data processing system (300) and computer readable medium operate in conjunction with the methods of the present invention. A method of making an integrated circuit (350) optimally places ties and connection elements within an integrated circuit design.
摘要翻译：用于在集成电路（120）内自动放置连接（136,138,146,148）和连接元件的方法（100,200,250）和数据处理系统（300）。针对特定集成电路（120）接收集成电路尺寸（102），元件位置和元件尺寸（104）以及连接放置规则（106）。然后处理这些量以将联系放置在集成电路（108）内。领带布置规则包括连接间距（164,166），边缘间距（162）和扩散间隔（168），以防止SCR闩锁和门限阈值电压漂移。绑带放置方法（100,200）自动地将联系放在集成电路（120）内以符合连接间隔规则，并且考虑估计的压缩，使得系数最小化。相关数据处理系统（300）和计算机可读介质结合本发明的方法进行操作。制造集成电路（350）的方法最佳地将联结和连接元件放置在集成电路设计中。

2. 发明授权

US5737236A Apparatus and method for the automatic determination of a standard library height within an integrated circuit design 失效
标题翻译：用于在集成电路设计中自动确定标准库高度的装置和方法
公开(公告)号：US5737236A
公开(公告)日：1998-04-07
申请号：US598555
申请日：1996-02-08
申请人： Robert Maziasz , Mohankumar Guruswamy , Daniel W. Dulitz , David Blaauw , Larry Jones
发明人： Robert Maziasz , Mohankumar Guruswamy , Daniel W. Dulitz , David Blaauw , Larry Jones
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： The present invention relates to a method (100, 150, 200) and associated data processing system (250) for determining a standard cell height within an integrated circuit design. A plurality of cell types, each cell type including a plurality of cell structures are received (102). Then, weighting values are received, one for each cell type (104). Expected intercell connection densities are preferably also received. Various target cell heights are processed with the plurality of cell types, the weighting values, and the expected intercell connection densities to generate a standard cell height (106). The standard cell height used with the integrated circuit design produces an optimized integrated circuit area, preferably a minimum area. The present invention includes a method (200) and system (250) for selecting an optimized standard cell height that, when used with a place-and-route tool to generate a physical design file (204) produces an optimized physical integrated circuit design. A method of manufacture (300) is also included.
摘要翻译：本发明涉及用于确定集成电路设计内的标准单元高度的方法（100,150,200）和相关联的数据处理系统（250）。接收多个小区类型，包括多个小区结构的每个小区类型（102）。然后，接收加权值，每个单元格类型（104）。也可以接收预期的小区间连接密度。用多个单元类型，加权值和预期的单元间连接密度来处理各个目标单元高度以产生标准单元高度（106）。与集成电路设计一起使用的标准单元格高度产生优化的集成电路面积，优选最小面积。本发明包括一种用于选择优化的标准单元高度的方法（200）和系统（250），当与用于生成物理设计文件（204）的放置和路径工具一起使用时，产生优化的物理集成电路设计。还包括制造方法（300）。

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