专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5381018A Electronic circuit to replace a light emitting diode and a light dependent resistor 失效
标题翻译：电子电路来代替发光二极管和光依赖电阻
公开(公告)号：US5381018A
公开(公告)日：1995-01-10
申请号：US169023
申请日：1993-12-20
申请人： Mohamad M. Mojaradi , Tuan A. Vo
发明人： Mohamad M. Mojaradi , Tuan A. Vo
IPC分类号： H01L31/10 , H01L31/12 , H03H11/02 , H03K17/10 , H03K17/14 , H03K17/785 , H03K17/795 , H03K3/42 , G02B27/00
CPC分类号： H03K17/102 , H03K17/785 , H03K17/7955
摘要： A variable impedance circuit in which an optoisolator transistor is controlled by an input light emitting diode to turn on a series of high voltage MOSFETs for use in applications currently using light emitting diode controlled with a light dependent resistor.
摘要翻译：一种可变阻抗电路，其中光隔离器晶体管由输入发光二极管控制，以接通一系列高电压MOSFET，用于目前使用由光依赖电阻器控制的发光二极管的应用中。

2. 发明授权

US5229308A Bipolar transistors with high voltage MOS transistors in a single substrate 失效
标题翻译：在单个衬底中具有高压MOS晶体管的双极晶体管
公开(公告)号：US5229308A
公开(公告)日：1993-07-20
申请号：US878141
申请日：1992-05-04
申请人： Tuan A. Vo , Mohamad M. Mojaradi , Steven A. Buhler
发明人： Tuan A. Vo , Mohamad M. Mojaradi , Steven A. Buhler
IPC分类号： H01L21/8249
CPC分类号： H01L21/8249 , Y10S148/009
摘要： A method of manufacturing a semiconductor device having a bipolar transistor for ordinary logic operation, as well as a high voltage MOS transistor which are provided in a single semiconductor substrate. The process includes the steps of making high voltage MOS transistors which comprises the steps of n-well fabrication, first drift region fabrication, second drift region fabrication, source and drain contact region fabrication and making bipolar transistors within the same silicon substrate as the high voltage MOS transistors which includes the step of base region fabrication where the steps for fabricating the second drift region of the high voltage MOS transistor and the base region of the bipolar transistor are combined so that both regions are created simultaneously.
摘要翻译：一种用于普通逻辑运算的半导体器件的制造方法以及设置在单个半导体衬底中的高压MOS晶体管。该方法包括制造高电压MOS晶体管的步骤，其包括以下步骤：n阱制造，第一漂移区制造，第二漂移区制造，源极和漏极接触区域制造以及在与高电压相同的硅衬底内制造双极晶体管 MOS晶体管包括基极区制造步骤，其中组合用于制造高压MOS晶体管的第二漂移区和双极晶体管的基极区的步骤，使得两个区域同时产生。

3. 发明授权

US5329147A High voltage integrated flyback circuit in 2 .mu.m CMOS 失效
标题翻译： 2 m CMOS CMOS高压集成回扫电路
公开(公告)号：US5329147A
公开(公告)日：1994-07-12
申请号：US000359
申请日：1993-01-04
申请人： Tuan A. Vo , Mohamad M. Mojaradi , Aram Nahidipour
发明人： Tuan A. Vo , Mohamad M. Mojaradi , Aram Nahidipour
IPC分类号： H01L27/02 , H01L27/082 , H01L29/72
CPC分类号： H01L27/0821 , H01L27/0248
摘要： When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.
摘要翻译：当使用场效应晶体管来控制通过电感负载的电流时，反激电压通过漏极上的垂直pnp晶体管感应到，该晶体管导通到衬底。该电流代表功率损耗和热源。本发明提供将该电流传导回电源的第二横向晶体管。

4. 发明授权

US5488301A Electrostatic voltmeter employing a differential cascode 失效
标题翻译：采用差分共源共栅的静电电压表
公开(公告)号：US5488301A
公开(公告)日：1996-01-30
申请号：US359170
申请日：1994-12-19
申请人： Alan J. Werner, Jr. , Mohamad M. Mojaradi , Mehrdad Zomorrodi , Steven A. Buhler , Tuan A. Vo
发明人： Alan J. Werner, Jr. , Mohamad M. Mojaradi , Mehrdad Zomorrodi , Steven A. Buhler , Tuan A. Vo
IPC分类号： G01R15/16 , G01R29/12 , G01R21/12
CPC分类号： G01R29/12 , G01R15/165
摘要： An electrostatic voltmeter suitable for use in a non-contacting, positive or negative potential sensing, type electrostatic voltmeter. The invention enables a flexible, low cost electrostatic voltmeter to be produced using high-voltage field-effect transistors in the circuit design. The invention further includes input conditioning components that enable high-voltage sensing and high-voltage feedback in such a manner that processing of the input signal from the sensor is accomplished without producing a variation in the current passing through the field-effect transistor in response to voltage variations. Elimination of this variation further reduces the susceptibility of the remaining signal processing circuitry to transient direct current signals. A differential cascode as the input stage is the preferred configuration for the input conditioning components.
摘要翻译：适用于非接触，正或负电位感应式静电电压表的静电电压表。本发明能够在电路设计中使用高电压场效应晶体管来制造灵活的，低成本的静电电压表。本发明还包括能够实现高电压感测和高电压反馈的输入调节部件，从而实现来自传感器的输入信号的处理，而不产生响应于通过场效应晶体管的电流的变化电压变化。消除这种变化进一步降低了剩余信号处理电路对瞬态直流信号的敏感性。作为输入级的差分共源共栅是输入调节部件的优选配置。

5. 发明授权

US5382826A Stacked high voltage transistor unit 失效
标题翻译：堆叠式高压晶体管单元
公开(公告)号：US5382826A
公开(公告)日：1995-01-17
申请号：US170848
申请日：1993-12-21
申请人： Mohamad M. Mojaradi , Tuan A. Vo
发明人： Mohamad M. Mojaradi , Tuan A. Vo
IPC分类号： H01L21/8234 , H01L23/482 , H01L27/088 , H01L29/06 , H01L29/40 , H01L29/78 , H03K17/10 , H01L23/58 , H01L29/76 , H03K17/687
CPC分类号： H01L29/405 , H01L23/4824 , H01L29/7816 , H03K17/102 , H01L2924/0002
摘要： A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.
摘要翻译：高电流，高电压晶体管，其可以容易地电堆叠以扩展电压范围，并且比传统的堆叠晶体管配置和具有最高欧姆值的最大击穿电压的场板的配置使用更少的硅面积。此外，星形场板设计提供最高的击穿电压和最高的欧姆值。现场板使用由手指连接的几个同心环构成，该同心环朝着同心环的中心更宽并且朝向同心环的周边变窄。

6. 发明授权

US5541439A Layout for a high voltage darlington pair 失效
标题翻译：布置高压达林顿对
公开(公告)号：US5541439A
公开(公告)日：1996-07-30
申请号：US341250
申请日：1994-11-17
申请人： Mohamad M. Mojaradi , Guillermo Lao , Steven A. Buhler , Tuan A. Vo
发明人： Mohamad M. Mojaradi , Guillermo Lao , Steven A. Buhler , Tuan A. Vo
IPC分类号： H01L27/082 , H01L23/58
CPC分类号： H01L27/0825
摘要： There is disclosed a layout of a high voltage Darlington pair in which a circular field plate is utilized for both high voltage transistors in order to reduce the layout area. In this layout, both transistors of a Darlington pair are circular transistors and they both have a common center. This enables both high voltage transistors to share one field plate ring and one collector ring.
摘要翻译：公开了高压达林顿对的布局，其中圆形场板用于两个高压晶体管，以便减小布局面积。在这种布局中，达林顿对的两个晶体管都是圆形晶体管，它们都具有共同的中心。这使得高压晶体管能够共享一个场板环和一个集电环。

7. 发明授权

US5349223A High current high voltage vertical PMOS in ultra high voltage CMOS 失效
标题翻译：超高电压CMOS中的大电流高压垂直PMOS
公开(公告)号：US5349223A
公开(公告)日：1994-09-20
申请号：US166400
申请日：1993-12-14
申请人： Mohamad M. Mojaradi , Tuan A. Vo , Steven A. Buhler
发明人： Mohamad M. Mojaradi , Tuan A. Vo , Steven A. Buhler
IPC分类号： H01L29/06 , H01L29/40 , H01L29/78 , H01L29/68
CPC分类号： H01L29/404 , H01L29/7802 , H01L29/7809
摘要： A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.
摘要翻译：采用标准工艺制造的具有给定第一载体类型的衬底的垂直晶体管，其具有独特的布局，其有利于高电压，高电流操作同时仍然节省空间。晶体管是利用内置在衬底的上部区域中的可重复组合栅极/源极区域构建的，使得在组合栅极/源极区域下方的衬底的剩余下部分是晶体管的漏极区域。

8. 发明授权

US5328859A Method of making high voltage PNP bipolar transistor in CMOS 失效
标题翻译：在CMOS中制造高压PNP双极晶体管的方法
公开(公告)号：US5328859A
公开(公告)日：1994-07-12
申请号：US357
申请日：1993-01-04
申请人： Tuan A. Vo , Mohamad M. Mojaradi
发明人： Tuan A. Vo , Mohamad M. Mojaradi
IPC分类号： H01L21/8238 , H01L29/08 , H01L21/265 , H01L29/70
CPC分类号： H01L21/8238 , H01L29/0804 , Y10S148/011
摘要： A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.
摘要翻译：制造在CMOS衬底上的高电压双极晶体管，而不需要增加任何额外的工艺步骤。在CMOS n阱掩模和注入步骤期间，为晶体管形成n阱。接下来，在CMOS场和深硼注入步骤期间，在n阱内形成圆形p场。最后，在CMOS p +掩模和注入步骤期间，形成p +发射极。发射极和n +基极之间的p场的存在提供高电压保护。

9. 发明授权

US5424226A Method of fabricating NMOS and PMOS FET's in a CMOS process 失效
标题翻译：在CMOS工艺中制造NMOS和PMOS FET的方法
公开(公告)号：US5424226A
公开(公告)日：1995-06-13
申请号：US225673
申请日：1994-04-11
申请人： Tuan A. Vo , Mohamad M. Mojaradi , Guillermo Lao
发明人： Tuan A. Vo , Mohamad M. Mojaradi , Guillermo Lao
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8249 , H01L21/266 , H01L21/8236
CPC分类号： H01L29/66575 , H01L21/823807 , H01L21/8249
摘要： A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.
摘要翻译：可以形成在硅衬底上并可在增强模式下工作的FET。 n +源极和漏极位于n阱内的中心，它们在栅极区域下方延伸，并分开一段距离。通过适当地选择n阱之间的距离，可以在同一芯片上的几个晶体管获得不同的阈值电压。

10. 发明授权

US5357393A Integrated ultra low leakage high voltage protection circuit 失效
标题翻译：集成超低漏电高压保护电路
公开(公告)号：US5357393A
公开(公告)日：1994-10-18
申请号：US878581
申请日：1992-05-05
申请人： Mohamad M. Mojaradi , Guillermo Lao , Dale Sumida
发明人： Mohamad M. Mojaradi , Guillermo Lao , Dale Sumida
IPC分类号： H01L27/02 , H02H3/20
CPC分类号： H01L27/0251
摘要： An integrated high voltage device with an ultra low leakage input protection circuit to be used in highly sensitive circuits which require ultra low input leakage current. The protection circuit has a common substrate with the integrated circuit device and the common substrate is floating. The floating substrate provides a way of designing a protection circuit with small diodes which have ultra low input D.C. leakage. The protection circuit includes a resistor and two small Zener diodes which can clamp and protect the device during normal operating conditions up to voltages such as 1700 volts.
摘要翻译：具有超低漏电输入保护电路的集成高压器件，用于需要超低输入漏电流的高灵敏电路。保护电路具有与集成电路器件相同的公共衬底，并且公共衬底浮动。浮置衬底提供了一种设计具有超低输入直流泄漏的小二极管保护电路的方法。保护电路包括一个电阻器和两个小的齐纳二极管，可在正常工作条件下钳制和保护器件，直到电压为1700伏。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式