专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5640329A Method of estimating heat generated in chip 失效
标题翻译：估计芯片产生的热量的方法
公开(公告)号：US5640329A
公开(公告)日：1997-06-17
申请号：US416309
申请日：1995-04-04
申请人： Mitsunori Matsunaga , Kiyotake Yoshimaru , Masateru Murakami
发明人： Mitsunori Matsunaga , Kiyotake Yoshimaru , Masateru Murakami
IPC分类号： H01L27/04 , G06F17/50 , H01L21/82 , H01L21/822
CPC分类号： G06F17/5022 , G06F17/5068
摘要： At Step S1, the circuit forming the semiconductor integrated circuit to be designed is divided into sub circuits, and the area sizes and the positions of blocks to seat the sub circuits are determined on a chip. At Step S2, only flip-flops are counted as cells which are assumed to be the source of heat. At Step S3, a heat quantity per unit area in each block (i.e., average heat quantity) is calculated for each sub circuit. More specifically, average heat quantities are calculated from the area sizes of the blocks, the number of the flip-flops of each sub circuit, and the amount of heat generated in each flip-flop during operation of the flip-flop. Heat generated in a semiconductor integrated circuit is estimated easily by considering only a clock signal.
摘要翻译：在步骤S1中，形成要设计的半导体集成电路的电路被分成子电路，并且在芯片上确定用于安置子电路的块的面积大小和位置。在步骤S2中，仅将触发器计为被认为是热源的单元。在步骤S3中，对于每个子电路计算每个块中每单位面积的热量（即，平均热量）。更具体地，根据块的面积大小，每个子电路的触发器的数量以及在触发器操作期间在每个触发器中产生的热量来计算平均热量。通过仅考虑时钟信号容易地估计在半导体集成电路中产生的热量。

2. 发明授权

US6072948A Device for rapid simulation of logic circuits 失效
标题翻译：逻辑电路快速仿真器件
公开(公告)号：US6072948A
公开(公告)日：2000-06-06
申请号：US17318
申请日：1998-02-02
申请人： Tetsuo Saitoh , Yuuji Okazaki , Mitsunori Matsunaga , Toshinori Inoshita
发明人： Tetsuo Saitoh , Yuuji Okazaki , Mitsunori Matsunaga , Toshinori Inoshita
IPC分类号： G06F9/455 , G06F17/50 , H01L21/82
CPC分类号： G06F17/5022
摘要： A logical simulation device has a delay value calculations section to calculate delay values of circuit blocks in a semiconductor integrated circuit as a target of logical simulation based on logical circuit information relating to the logical circuit blocks, input test patterns as operational descriptions of used in circuit verification, and delay value calculation information stored in a delay value and timing check value calculation library, and a logical simulation section performs the logical simulation of the semiconductor integrated circuit based on the calculated delay values.
摘要翻译：逻辑模拟装置具有延迟值计算部分，用于基于与逻辑电路块相关的逻辑电路信息计算半导体集成电路中的电路块的延迟值作为逻辑仿真的目标，输入测试图案作为电路中使用的操作描述验证和延迟值计算信息存储在延迟值和定时检查值计算库中，并且逻辑模拟部分基于所计算的延迟值来执行半导体集成电路的逻辑模拟。

3. 发明申请

US20050146337A1 Method of manufacturing and testing semiconductor device using assembly substrate 审中-公开
标题翻译：使用组装基板制造和测试半导体器件的方法
公开(公告)号：US20050146337A1
公开(公告)日：2005-07-07
申请号：US11055627
申请日：2005-02-11
申请人： Mitsunori Matsunaga , Tsugumi Matsuishi
发明人： Mitsunori Matsunaga , Tsugumi Matsuishi
IPC分类号： G01R31/26 , G01R1/04 , G01R31/28 , G01R31/30 , H01L21/66 , G01R31/02
CPC分类号： G01R31/2863 , G01R1/0408
摘要： A method of manufacturing a semiconductor device including mounting semiconductor chips, each chip having pads, on respective areas of a front surface of an assembly substrate, electrically connecting corresponding terminals on a rear surface of the assembly substrate through wirings of the assembly substrate to the pads of the semiconductor chips, respective terminals and wirings electrically connected to a semiconductor chip being confined within the corresponding area of the assembly substrate on which the semiconductor chip is mounted, inputting test waveforms to the pads of the plurality of semiconductor chips through the corresponding terminals and wirings and testing the semiconductor chips, and, after the testing the semiconductor chips, cutting the assembly substrate with a rotating blade into pieces corresponding to the respective areas. The terminals and wirings connecting the terminals to the semiconductor chips are not cut by the rotating blade.
摘要翻译：一种制造半导体器件的方法，包括在组件衬底的前表面的相应区域上安装半导体芯片，每个芯片具有衬垫，通过组装衬底的布线将电连接到组件衬底的后表面上的相应端子，将与半导体芯片电连接的各个端子和布线限制在其上安装有半导体芯片的组装衬底的相应区域内，通过相应的端子向多个半导体芯片的焊盘输入测试波形，以及布线并测试半导体芯片，并且在测试半导体芯片之后，用旋转叶片将组装衬底切割成与各个区域相对应的片段。将端子与半导体芯片连接的端子和配线不会被旋转刀片切断。

4. 发明申请

US20050098778A1 Burn-in test adapter and burn-in test apparatus 审中-公开
标题翻译：老化测试适配器和老化测试仪器
公开(公告)号：US20050098778A1
公开(公告)日：2005-05-12
申请号：US10615243
申请日：2003-07-09
申请人： Mitsunori Matsunaga , Tsugumi Matsuishi
发明人： Mitsunori Matsunaga , Tsugumi Matsuishi
IPC分类号： G01R31/26 , G01R1/04 , G01R31/28 , G01R31/30 , H01L21/66
CPC分类号： G01R31/2863 , G01R1/0408
摘要： An assembly substrate, on which semiconductor chips, each having a terminal receiving a burn-in test waveform, are arranged, is detachably attached to a burn-in test adapter. The burn-in test adapter has wiring for, when an assembly substrate is attached to the burn-in test adapter, making an electrical contact with the terminal of each of the semiconductor chips on the assembly substrate. Moreover, the burn-in test adapter has a burn-in test terminal that is electrically connected to the wiring and that receives the burn-in test waveform.
摘要翻译：布置有其上各自具有接收老化测试波形的端子的半导体芯片的组装衬底可拆卸地附接到老化测试适配器。老化测试适配器具有用于当将组装衬底附接到老化测试适配器时，与组装衬底上的每个半导体芯片的端子电接触的布线。此外，老化测试适配器具有电连接到布线并且接收老化测试波形的老化测试端子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式