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1. 发明申请

US20070187777A1 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US20070187777A1
公开(公告)日：2007-08-16
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/76 , G06F17/50
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

2. 发明申请

US20050017320A1 Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device 有权
标题翻译：半导体器件的半导体器件图案方法和半导体器件的图案发生器的半导体器件方法
公开(公告)号：US20050017320A1
公开(公告)日：2005-01-27
申请号：US10496297
申请日：2002-11-21
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/02 , H01L27/04 , H01L29/00 , H01L27/108 , H01L29/94
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit. The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

3. 发明授权

US07911027B2 Semiconductor device, method of generating pattern for semiconductor device, method of manufacturing semiconductor device, and apparatus for generating pattern for semiconductor device 有权
标题翻译：半导体装置，半导体装置的图形生成方法，半导体装置的制造方法以及半导体装置的图案生成装置
公开(公告)号：US07911027B2
公开(公告)日：2011-03-22
申请号：US11783465
申请日：2007-04-10
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

4. 发明授权

US07307333B2 Semiconductor device method of generating semiconductor device pattern method of semiconductor device and pattern generator for semiconductor device 有权
标题翻译：半导体器件的半导体器件图案方法和半导体器件的图案发生器的半导体器件方法
公开(公告)号：US07307333B2
公开(公告)日：2007-12-11
申请号：US10496297
申请日：2002-11-21
申请人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
发明人： Mitsumi Itoh , Masatoshi Sawada , Junko Honma , Kenji Shimazaki , Hiroyuki Tsujikawa , Hiroshi Benno
IPC分类号： H01L29/00
CPC分类号： H01L27/0207 , G06F17/5068
摘要： It is an object of the invention to effectively absorb a power noise and to implement the stable operation of a circuit.The invention provides a semiconductor device comprising a bypass capacitor including an MOS structure having a gate electrode formed to be extended from a power wiring region to a portion provided under an empty region which is adjacent to the power wiring region and has no other functional layer, and formed through a capacitive insulating film on a diffusion region having one conductivity type, and a substrate contact formed under a ground wiring region and fixing a substrate potential, wherein the bypass capacitor has a contact to come in contact with the power wiring which is formed on a surface of the gate electrode and has the diffusion region having the one conductivity type and a diffusion region of the substrate contact connected to each other.
摘要翻译：本发明的目的是有效地吸收电力噪声并实现电路的稳定操作。本发明提供了一种半导体器件，包括：旁路电容器，其包括具有形成为从电力布线区域延伸到与电力布线区域相邻的空白区域下方的部分的MOS电结构，并且不具有其他功能层，并且通过在一个导电类型的扩散区域上的电容绝缘膜形成，以及形成在接地布线区域下方并固定衬底电位的衬底接触，其中旁路电容器具有与形成的电源布线接触的接触在栅电极的表面上形成具有一个导电类型的扩散区域和基板接触的扩散区域彼此连接。

5. 发明申请

US20060091550A1 Method of analyzing operation of semiconductor integrated circuit device, analyzing apparatus used in the same, and optimization designing method using the same 审中-公开
标题翻译：分析半导体集成电路装置的运行方法，使用的分析装置以及使用其的优化设计方法
公开(公告)号：US20060091550A1
公开(公告)日：2006-05-04
申请号：US11231810
申请日：2005-09-22
申请人： Kenji Shimazaki , Kazuhiro Satoh , Hiroyuki Tsujikawa , Shouzou Hirano , Makoto Nagata
发明人： Kenji Shimazaki , Kazuhiro Satoh , Hiroyuki Tsujikawa , Shouzou Hirano , Makoto Nagata
IPC分类号： H01L23/52
CPC分类号： G06F17/5031
摘要： In a method of analyzing a power noise based on the circuit information of a semiconductor integrated circuit device, the power noise is analyzed in consideration of the influence of the impedance of a substrate. Consequently, the impedance of the substrate which has not been conventionally considered is taken into consideration. Thus, precision in the analysis can be enhanced more greatly.
摘要翻译：在基于半导体集成电路器件的电路信息分析功率噪声的方法中，考虑到衬底的阻抗的影响来分析功率噪声。因此，考虑到未经常考虑的基板的阻抗。因此，分析的精度可以更大的提高。

6. 发明授权

US06959250B1 Method of analyzing electromagnetic interference 失效
标题翻译：分析电磁干扰的方法
公开(公告)号：US06959250B1
公开(公告)日：2005-10-25
申请号：US09615938
申请日：2000-07-13
申请人： Kenji Shimazaki , Hiroyuki Tsujikawa , Seijirou Kojima , Shouzou Hirano
发明人： Kenji Shimazaki , Hiroyuki Tsujikawa , Seijirou Kojima , Shouzou Hirano
IPC分类号： G01R29/08 , G01R23/00 , G01R23/04 , G06F17/50 , H01L29/00
CPC分类号： G06F17/5036 , Y02T10/82
摘要： In contrast with a known dynamic gate-level simulation method, a method of analyzing electromagnetic interference (an EMI analysis method) according to the present invention enables estimation of EMI noise, by means of calculating signal propagation of each node through use of the signal propagation probability technique, and calculating variation time of each node through use of “the Static timing analysis technique”. In short, the present invention is characterized in calculating a frequency characteristic from the relationship between toggle probability of each node and delay in each node.
摘要翻译：与已知的动态门级仿真方法相反，根据本发明的分析电磁干扰（EMI分析方法）的方法能够通过使用信号传播来计算每个节点的信号传播来估计EMI噪声概率技术，并通过使用“静态时序分析技术”来计算每个节点的变化时间。简而言之，本发明的特征在于根据每个节点的触发概率与每个节点的延迟之间的关系来计算频率特性。

7. 发明申请

US20050114054A1 Method for analyzing power supply noise of semiconductor integrated circuit 审中-公开
标题翻译：分析半导体集成电路电源噪声的方法
公开(公告)号：US20050114054A1
公开(公告)日：2005-05-26
申请号：US10988833
申请日：2004-11-16
申请人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
发明人： Kenji Shimazaki , Kazuhiro Sato , Takahiro Ichinomiya , Shozo Hirano , Masao Takahashi , Hiroyuki Tsujikawa , Seijiro Kojima
IPC分类号： G06F17/50 , G01R29/26 , H01L21/82 , H01L21/822 , H01L27/04 , H03K17/16
CPC分类号： G01R29/26
摘要： Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.
摘要翻译：基于半导体集成电路的设计数据，计算与电源线相关的阻抗，并且基于所计算的阻抗来分析电源噪声的频率特性。在计算阻抗时，可以计算电位不同的电源之间的阻抗，例如主电源和接地。或者，可以计算电位基本相同的电源之间的阻抗，例如主电源和N阱电源。所计算的阻抗包括电源线之间的线电容，衬底电阻，连接到电源线的封装的阻抗等。因此，可以提供一种用于分析半导体集成电路的电源噪声的方法，其可以在少量计算的设计过程的早期阶段执行。

8. 发明授权

US06876210B2 Method and apparatus for analyzing electromagnetic interference 失效
标题翻译：用于分析电磁干扰的方法和装置
公开(公告)号：US06876210B2
公开(公告)日：2005-04-05
申请号：US09993595
申请日：2001-11-27
申请人： Kenji Shimazaki , Shouzou Hirano , Tatsuo Ohhashi , Takashi Mizokawa , Hiroyuki Tsujikawa
发明人： Kenji Shimazaki , Shouzou Hirano , Tatsuo Ohhashi , Takashi Mizokawa , Hiroyuki Tsujikawa
IPC分类号： G01R29/08 , G01R31/00 , G01R31/28 , G06F17/50 , H01L21/82 , G01R31/302
CPC分类号： G06F17/5022 , G01R31/002
摘要： A method of analyzing electromagnetic interference in which an amount of electromagnetic interference from an LSI is analyzed, wherein the method includes: an equivalent power source current information calculating step of calculating information of an equivalent power source current flowing in a power source current, from circuit information of the LSI chip; an estimating step of considering at least one of power source information of a power source for supplying a current to the LSI chip, package information of a package for the semiconductor chip, and measurement system information of a measurement system for measuring characteristics of the semiconductor chip, as analysis control information, and of estimating total information in which the analysis control information is reflected in the circuit information, as an equivalent circuit; and a total information analyzing step of performing analysis in accordance with the total information which is estimated in the estimating step.
摘要翻译：一种分析其中分析来自LSI的电磁干扰量的电磁干扰的方法，其中所述方法包括：等效电源电流信息计算步骤，从电路中计算流过电源电流的等效电源电流的信息， LSI芯片的信息; 考虑将用于向LSI芯片提供电流的电源的电源信息，半导体芯片的封装的封装信息以及用于测量半导体芯片的特性的测量系统的测量系统信息中的至少一个的估计步骤作为分析控制信息，并且将分析控制信息反映在电路信息中的总信息估计为等效电路; 以及总信息分析步骤，根据在估计步骤中估计的总信息进行分析。

9. 发明授权

US06782347B2 Method for optimizing electromagnetic interference and method for analyzing the electromagnetic interference 有权
标题翻译：电磁干扰优化方法及电磁干扰分析方法
公开(公告)号：US06782347B2
公开(公告)日：2004-08-24
申请号：US09993965
申请日：2001-11-27
申请人： Shouzou Hirano , Takashi Mizokawa , Tatsuo Ohhashi , Kenji Shimazaki , Hiroyuki Tsujikawa
发明人： Shouzou Hirano , Takashi Mizokawa , Tatsuo Ohhashi , Kenji Shimazaki , Hiroyuki Tsujikawa
IPC分类号： G06F308
CPC分类号： G06F17/5036 , Y02T10/82
摘要： A method for optimizing electromagnetic interference (EMI) comprising: an EMI analyzing step of analyzing a quantity of electromagnetic interference of an LSI by execution of simulation; a step of selecting an instance with a large quantity of noise in said EMI analyzing step; and a step of adjusting a driving capability of said instance so that it is lowered to an extent that a delay does not occur in a signal timing of said instance selected. In order to optimize the analyzed EMI, the portion for which optimizing is required is extracted, and such a measure as increasing the area where the decoupling capacitance is created is implemented for this portion in a necessary degree. Further, by changing the aspect ratio of the block, changing the block position or changing the cell line, the decoupling capacitance can be easily created at the most efficient inserting position.
摘要翻译：一种用于优化电磁干扰（EMI）的方法，包括：EMI分析步骤，通过执行仿真分析LSI的电磁干扰量; 在所述EMI分析步骤中选择具有大量噪声的实例的步骤; 以及调整所述实例的驱动能力以使其降低到在所选择的所述实例的信号定时中不发生延迟的程度的步骤。为了优化分析的EMI，提取需要优化的部分，并且在必要的程度上对该部分实现增加去耦电容的面积增加的措施。此外，通过改变块的纵横比，改变块位置或改变单元行，可以在最有效的插入位置容易地创建去耦电容。

10. 发明授权

US06754598B2 Electromagnetic interference analysis method and apparatus 有权
标题翻译：电磁干扰分析方法及装置
公开(公告)号：US06754598B2
公开(公告)日：2004-06-22
申请号：US10193734
申请日：2002-07-12
申请人： Kenji Shimazaki , Shouzou Hirano , Hiroyuki Tsujikawa
发明人： Kenji Shimazaki , Shouzou Hirano , Hiroyuki Tsujikawa
IPC分类号： G06F1900
CPC分类号： G01R31/002 , Y02T10/82
摘要： A method of analyzing an electromagnetic interference amount of an LSI includes an equivalent impedance information calculating step of calculating and estimating equivalent impedance information based on circuit information of an LSI chip and package information of the LSI chip, and an electromagnetic interference noise calculating step of calculating an electromagnetic interference noise based on the equivalent impedance information.
摘要翻译：分析LSI的电磁干扰量的方法包括：等效阻抗信息计算步骤，其基于LSI芯片的电路信息和LSI芯片的封装信息来计算和估计等效阻抗信息;以及电磁干扰噪声计算步骤，计算基于等效阻抗信息的电磁干扰噪声。

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