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1. 发明申请

US20090096007A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20090096007A1
公开(公告)日：2009-04-16
申请号：US12244523
申请日：2008-10-02
申请人： Mitsuhiro OMURA , Satoshi NAGASHIMA , Katsunori YAHASHI , Jungo INABA , Daina INOUE
发明人： Mitsuhiro OMURA , Satoshi NAGASHIMA , Katsunori YAHASHI , Jungo INABA , Daina INOUE
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.
摘要翻译：半导体存储器件包括具有层叠栅结构的多个晶体管。每个晶体管包括半导体衬底，形成在半导体衬底上的栅极绝缘体，形成在半导体衬底上的栅极绝缘体插入的下栅极，形成在下栅极上的栅极绝缘体和在下栅极上形成并硅化的上栅极间隔绝缘体插入。晶体管的一部分具有通过栅极间绝缘体形成的孔，以将下栅极与上栅极连接，并且还包括由绝缘体构成并形成为小于上栅极且大于上栅极上方的孔的阻挡膜以覆盖光圈。

2. 发明申请

US20120032247A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20120032247A1
公开(公告)日：2012-02-09
申请号：US13197263
申请日：2011-08-03
申请人： Satoshi NAGASHIMA , Junya Fujita , Hideyuki Yamawaki , Masahiro Kiyotoshi , Hisataka Meguro
发明人： Satoshi NAGASHIMA , Junya Fujita , Hideyuki Yamawaki , Masahiro Kiyotoshi , Hisataka Meguro
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L27/11526 , H01L27/11529 , H01L29/42324
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].
摘要翻译：根据一个实施例，非易失性半导体存储器件包括通过在沟道半导体层上依次层叠栅绝缘膜，浮栅电极，电极间绝缘膜和控制栅电极而获得的存储单元晶体管。控制栅电极具有通过顺序堆叠半导体膜，硅化物相变抑制层和硅化物膜而获得的结构。此外，硅化物相变抑制层包括在1×1020〜5×1021 [原子/ cm3]的浓度范围内掺杂有C，F和N中的至少一种的多晶硅膜。

3. 发明申请

US20130248968A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD 有权
标题翻译：非线性半导体存储器件及其制造方法
公开(公告)号：US20130248968A1
公开(公告)日：2013-09-26
申请号：US13606757
申请日：2012-09-07
申请人： Satoshi NAGASHIMA , Fumitaka ARAI , Hisataka MEGURO
发明人： Satoshi NAGASHIMA , Fumitaka ARAI , Hisataka MEGURO
IPC分类号： H01L27/088 , H01L21/28
CPC分类号： H01L21/28273 , G11C16/0408 , H01L27/11524 , H01L27/11551 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A nonvolatile semiconductor memory device a first memory cell array layer, a first insulation layer formed on top of the first memory cell array layer, a second memory cell array layer formed on the first insulation layer, and a control gate. The first and second memory cell array layers have first and second NAND cell units provided with multiple first and second memory cells connected in series in a first direction and the first and second selection gates connected at both ends of the multiple first and second memory cells. The control gate is formed via an insulation layer between gates of the memory cells on both sides thereof in the first direction, and extends in the second direction perpendicular to the first direction.
摘要翻译：非易失性半导体存储器件，第一存储单元阵列层，形成在第一存储单元阵列层顶部的第一绝缘层，形成在第一绝缘层上的第二存储单元阵列层和控制栅极。第一和第二存储单元阵列层具有第一和第二NAND单元单元，其具有在第一方向上串联连接的多个第一和第二存储单元，并且第一和第二选择栅极连接在多个第一和第二存储单元的两端。控制栅极是通过在其第一方向的两侧的存储单元的栅极之间的绝缘层形成的，并且在垂直于第一方向的第二方向上延伸。

4. 发明申请

US20130228844A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20130228844A1
公开(公告)日：2013-09-05
申请号：US13601468
申请日：2012-08-31
申请人： Satoshi NAGASHIMA , Fumitaka Arai , Hisataka Meguro
发明人： Satoshi NAGASHIMA , Fumitaka Arai , Hisataka Meguro
IPC分类号： H01L27/088 , H01L21/28 , H01L29/788
CPC分类号： H01L27/088 , H01L21/28273 , H01L27/11524 , H01L27/11551 , H01L29/788 , H01L29/7881
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.
摘要翻译：根据实施例的非易失性半导体存储器件包括多个单元阵列层，每个单元阵列层包括：沿第一方向延伸的多个半导体层; 栅绝缘层; 沿所述第一方向布置的多个浮动栅极; 栅极间绝缘层; 以及多个控制栅极，其在与半导体层交叉的第二方向上延伸，并且经由所述栅极间绝缘层面向所述浮置栅极，其中，在层叠方向上彼此相邻的所述单元阵列层中，所述控制栅极下单元阵列层和上单元阵列层的控制栅极彼此相交，并且下单元阵列层内的浮置栅极和上单元阵列层内的半导体层彼此对准。

5. 发明申请

US20130020629A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20130020629A1
公开(公告)日：2013-01-24
申请号：US13557295
申请日：2012-07-25
申请人： Kyoko ANDO , Satoshi NAGASHIMA , Kenji AOYAMA
发明人： Kyoko ANDO , Satoshi NAGASHIMA , Kenji AOYAMA
IPC分类号： H01L29/788
CPC分类号： H01L29/42324 , H01L21/76229 , H01L27/105 , H01L27/11526 , H01L27/11529 , H01L29/66825 , H01L29/7883
摘要： According to one embodiment, a semiconductor memory device includes a plurality of word lines formed on a semiconductor substrate at predetermined intervals, selecting transistors arranged on at least one side of the plurality of word lines, an interlayer insulating film formed to cover upper surfaces of the word lines and the selecting transistors, a first air gap located between each pair of adjacent ones of the word lines and covered by the interlayer insulating film, a second air gap located at a first side wall portion of a word line adjacent to the selecting transistors covered by the interlayer insulating film, the first side wall portion facing the selecting transistors, and a third air gap located at a second side wall portion of each of the selecting transistors and covered by the interlayer insulating film. The first, second, and third air gaps are filled with air.
摘要翻译：根据一个实施例，半导体存储器件包括以预定间隔形成在半导体衬底上的多个字线，选择排列在多个字线的至少一侧的晶体管，形成为覆盖所述多个字线的上表面的层间绝缘膜字线和选择晶体管，位于每对相邻字线之间并由层间绝缘膜覆盖的第一气隙，位于与选择晶体管相邻的字线的第一侧壁部分处的第二气隙被层间绝缘膜覆盖，面向选择晶体管的第一侧壁部分和位于每个选择晶体管的第二侧壁部分并被层间绝缘膜覆盖的第三气隙。第一，第二和第三气隙充满空气。

6. 发明申请

US20100320525A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
标题翻译：非易失性半导体存储器件的制造方法和非易失性半导体存储器件的制造方法
公开(公告)号：US20100320525A1
公开(公告)日：2010-12-23
申请号：US12611640
申请日：2009-11-03
申请人： Satoshi NAGASHIMA , Nobuhito KAWADA
发明人： Satoshi NAGASHIMA , Nobuhito KAWADA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/1211 , H01L27/11568 , H01L27/11578 , H01L29/4234 , H01L29/792
摘要： A nonvolatile semiconductor memory device includes: fin-shaped control gate electrodes formed on an insulating layer; and a body layer having a channel region arranged to cross the control gate electrodes and embedded in the control gate electrodes sequentially via a first insulating layer, a charge storage layer, and a second insulating layer.
摘要翻译：非易失性半导体存储器件包括：形成在绝缘层上的鳍状控制栅电极; 以及体层，具有布置成经由第一绝缘层，电荷存储层和第二绝缘层顺序地跨越控制栅极并嵌入控制栅电极的沟道区。

7. 发明申请

US20130237051A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20130237051A1
公开(公告)日：2013-09-12
申请号：US13602841
申请日：2012-09-04
申请人： Keisuke KIKUTANI , Satoshi NAGASHIMA , Hidefumi MUKAI , Takehiro KONDOH , Hisataka MEGURO
发明人： Keisuke KIKUTANI , Satoshi NAGASHIMA , Hidefumi MUKAI , Takehiro KONDOH , Hisataka MEGURO
IPC分类号： H01L21/768
CPC分类号： H01L21/76801 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L27/11519 , H01L27/11524 , H01L27/11548 , H01L27/11565 , H01L27/1157 , H01L27/11575
摘要： According to one embodiment, a method of manufacturing a device, includes forming a first core including a line portion extending between first and second regions and having a first width and a fringe having a dimension larger than the first width, forming a mask on the fringe and on a first sidewall on the first core, removing the first core so that a remaining portion having a dimension larger than the first width is formed below the mask, forming a second sidewall on a pattern corresponding the first sidewall and the remaining portion, the second sidewall having a second width less than the first width and facing a first interval less than the first width in the first region and facing a second interval larger than the first interval in the second region.
摘要翻译：根据一个实施例，一种制造器件的方法包括形成包括在第一和第二区域之间延伸的线部分并具有第一宽度和具有大于第一宽度的尺寸的条纹的第一芯体，在边缘上形成掩模并且在所述第一芯上的第一侧壁上，移除所述第一芯，使得具有大于所述第一宽度的尺寸的剩余部分形成在所述掩模下方，在对应于所述第一侧壁和所述剩余部分的图案上形成第二侧壁，第二侧壁具有小于第一宽度的第二宽度并且面向小于第一区域中的第一宽度的第一间隔并且面向大于第二区域中的第一间隔的第二间隔。

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