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1. 发明授权

US08542041B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US08542041B2
公开(公告)日：2013-09-24
申请号：US12755119
申请日：2010-04-06
申请人： Mitsuhiro Ogai , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
发明人： Mitsuhiro Ogai , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
IPC分类号： H03L7/00
CPC分类号： G11C5/147
摘要： A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
摘要翻译：第一晶体管具有耦合到第一电源线和耦合到第一节点的另一端的一端和栅极。第二晶体管具有耦合到第二节点的栅极，耦合到第一节点的一端和耦合到第三节点的另一端。第三晶体管具有耦合到第二电源线的一端，耦合到第四节点的栅极和耦合到第三节点的另一端。第一偏置电压产生电路向第二节点提供第一偏置电压。第二偏置电压产生电路向第四节点提供第二偏置电压。因此，第三节点从一定电平变化到另一电平的电源电压被设定为高电平，并且当电源电压降低时半导体器件中的内部节点被可靠地初始化。

2. 发明申请

US20100253419A1 SEMICONDUCTOR DEVICE AND SYSTEM 有权
标题翻译：半导体器件和系统
公开(公告)号：US20100253419A1
公开(公告)日：2010-10-07
申请号：US12755119
申请日：2010-04-06
申请人： Mitsuhiro OGAI , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
发明人： Mitsuhiro OGAI , Hirokazu Yamazaki , Keizo Morita , Kazuaki Yamane , Yasuhiro Fujii , Kazuaki Takai , Shoichiro Kawashima
IPC分类号： G05F3/02
CPC分类号： G11C5/147
摘要： A first transistor has one end and a gate coupled to a first power supply line and other end coupled to a first node. A second transistor has a gate coupled to a second node, one end coupled to the first node, and other end coupled to a third node. A third transistor has one end coupled to a second power supply line, a gate coupled to a fourth node, and other end coupled to the third node. A first bias voltage generation circuit supplies a first bias voltage to the second node. A second bias voltage generation circuit supplies a second bias voltage to the fourth node. Accordingly, the power supply voltage at which the third node is changed from a certain level to another level is set high, and an internal node in a semiconductor device is securely initialized when the power supply voltage is decreased.
摘要翻译：第一晶体管具有耦合到第一电源线和耦合到第一节点的另一端的一端和栅极。第二晶体管具有耦合到第二节点的栅极，耦合到第一节点的一端和耦合到第三节点的另一端。第三晶体管具有耦合到第二电源线的一端，耦合到第四节点的栅极和耦合到第三节点的另一端。第一偏置电压产生电路向第二节点提供第一偏置电压。第二偏置电压产生电路向第四节点提供第二偏置电压。因此，第三节点从一定电平变化到另一电平的电源电压被设定为高电平，并且当电源电压降低时半导体器件中的内部节点被可靠地初始化。

3. 发明授权

US07525846B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US07525846B2
公开(公告)日：2009-04-28
申请号：US11485553
申请日：2006-07-13
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/03
CPC分类号： G11C11/22
摘要： A memory device includes a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.
摘要翻译：一种存储器件，包括具有根据数据逻辑累积电荷的电容器的存储单元，连接到存储单元的位线，用于将位线中的电荷传送到输出节点的电荷转移电路，连接到位线的虚拟存储单元，以及用于根据位线的电压变化来控制电荷转移电路的电荷转移能力的控制电路。

4. 发明申请

US20070217250A1 Memory device 有权
标题翻译：内存设备
公开(公告)号：US20070217250A1
公开(公告)日：2007-09-20
申请号：US11485553
申请日：2006-07-13
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： There is provided a memory device including a memory cell having a capacitor for accumulating electric charges in accordance with the logic of data, a bit line connected to the memory cell, a charge transfer circuit for transferring the electric charges in the bit line to an output node, a dummy memory cell connected to the bit line, and a control circuit for controlling the charge transfer ability of the charge transfer circuit in accordance with the change in the voltage of the bit line.
摘要翻译：提供了一种存储器件，其包括具有根据数据逻辑累积电荷的电容器的存储单元，连接到存储单元的位线，用于将位线中的电荷转移到输出的电荷转移电路节点，连接到位线的虚拟存储单元，以及控制电路，用于根据位线电压的变化来控制电荷转移电路的电荷转移能力。

5. 发明授权

US07729181B2 Semiconductor storage device using a bitline GND sensing scheme for a reduced real estate of pre-sense amplifier 有权
标题翻译：半导体存储设备使用位线GND感测方案，用于预读取放大器的减少的空间
公开(公告)号：US07729181B2
公开(公告)日：2010-06-01
申请号：US11653909
申请日：2007-01-17
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C7/06
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.
摘要翻译：半导体存储装置包括连接到板线和位线的存储单元，连接到位线的电位移动电路在施加电压时临时改变与位线的电压变化相对应的输出电压用于传送与电位移动电路的临时输出电压变化相对应的存储在电位移位电路上的电荷的电荷转移电路，以及用于在累积转移电荷之后从存储单元产生读取电压的电荷累积电路。

6. 发明申请

US20090168577A1 SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD 审中-公开
标题翻译：半导体存储器件和数据读取方法
公开(公告)号：US20090168577A1
公开(公告)日：2009-07-02
申请号：US12398816
申请日：2009-03-05
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C7/02
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.
摘要翻译：半导体存储装置包括连接到板线和位线的存储单元，连接到位线的电位移动电路在施加电压时临时改变与位线的电压变化相对应的输出电压然后在对板线施加电压之前输出电压;电荷转移电路，用于转移与电位移动电路的临时输出电压变化对应的电位移位电路上存储的电荷，以及电荷累积电路，用于在累积传送的电荷之后从存储单元产生读取电压。

7. 发明授权

US07483287B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07483287B2
公开(公告)日：2009-01-27
申请号：US11790529
申请日：2007-04-26
申请人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
发明人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.
摘要翻译：位线通过电荷转移电路连接到电荷存储电路。控制电路根据从存储单元读出的电荷产生的位线的电压变化来控制电荷转移电路的电荷转移能力。泄漏控制电路在电荷被读出到位线之前暂时在读取操作中降低电荷转移电路的电荷转移能力。泄漏控制电路使得可以避免在从存储单元读取数据之前电荷存储电路和位线之间的电荷转移。因此，电荷存储电路可以根据存储在存储单元中的数据的逻辑值产生足以使读取电路工作的读取电压。

8. 发明申请

US20080055960A1 Semiconductor storage device, and data reading method 有权
标题翻译：半导体存储器件和数据读取方法
公开(公告)号：US20080055960A1
公开(公告)日：2008-03-06
申请号：US11653909
申请日：2007-01-17
申请人： Keizo Morita , Shoichiro Kawashima
发明人： Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A semiconductor storage device comprises of a memory cell connected to a plate line and a bit line, a potential shift circuit which is connected to a bit line, temporarily changes in output voltage corresponding to the voltage change of the bit line when a voltage is applied to the plate line, and then outputs a voltage before the application of the voltage to the plate line, a charge transfer circuit for transferring charge stored on the potential shift circuit corresponding to the temporary output voltage change of the potential shift circuit, and a charge accumulation circuit for generating a read voltage from a memory cell after accumulating the transferred charge.
摘要翻译：半导体存储装置包括连接到板线和位线的存储单元，连接到位线的电位移动电路在施加电压时临时改变与位线的电压变化相对应的输出电压然后在对板线施加电压之前输出电压;电荷转移电路，用于转移与电位移动电路的临时输出电压变化对应的电位移位电路上存储的电荷，以及电荷累积电路，用于在累积传送的电荷之后从存储单元产生读取电压。

9. 发明申请

US20070195579A1 Semiconductor memory 有权
公开(公告)号：US20070195579A1
公开(公告)日：2007-08-23
申请号：US11790529
申请日：2007-04-26
申请人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
发明人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.

10. 发明授权

US07227769B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07227769B2
公开(公告)日：2007-06-05
申请号：US11073036
申请日：2005-03-07
申请人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
发明人： Isao Fukushi , Keizo Morita , Shoichiro Kawashima
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C29/02 , G11C29/026 , G11C29/028 , G11C2029/1204
摘要： A bit line is connected to a charge storing circuit through a charge transferring circuit. A control circuit controls charge transferability of the charge transferring circuit according to a change in the voltage of the bit line resulting from a charge read out from a memory cell. A leakage controlling circuit lowers the charge transferability of the charge transferring circuit in a read operation temporarily before the charge is read out to the bit line. The leakage controlling circuit makes it possible to avoid charge transfer between the charge storing circuit and the bit line before data is read from the memory cell. The charge storing circuit can thus generate a read voltage sufficient for a read circuit to operate with, in accordance with the logical value of the data stored in the memory cell.
摘要翻译：位线通过电荷转移电路连接到电荷存储电路。控制电路根据从存储单元读出的电荷产生的位线的电压变化来控制电荷转移电路的电荷转移能力。泄漏控制电路在电荷被读出到位线之前暂时在读取操作中降低电荷转移电路的电荷转移能力。泄漏控制电路使得可以避免在从存储单元读取数据之前电荷存储电路和位线之间的电荷转移。因此，电荷存储电路可以根据存储在存储单元中的数据的逻辑值产生足以使读取电路工作的读取电压。

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