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1. 发明授权

US11217449B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US11217449B2
公开(公告)日：2022-01-04
申请号：US16587197
申请日：2019-09-30
申请人： Mitsubishi Electric Corporation
发明人： Tomohide Terashima , Yasuhiro Kagawa , Kensuke Taguchi
IPC分类号： H01L21/22 , H01L29/10 , H01L29/16 , H01L29/32 , H01L29/78 , H01L29/66 , H01L29/739
摘要： There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

2. 发明授权

US11552073B2 Semiconductor device 有权
公开(公告)号：US11552073B2
公开(公告)日：2023-01-10
申请号：US17453530
申请日：2021-11-04
申请人： Mitsubishi Electric Corporation
发明人： Sho Tanaka , Tomohide Terashima
IPC分类号： H01L27/02 , H03K17/082 , H02H9/02
摘要： A semiconductor device includes a main IGBT, a sense, a resistor, a MOSFET and a diode, as main components. The sense IGBT and the main IGBT are connected in parallel with each other. The drain of MOSFET is connected to the gate of the sense IGBT, the source thereof is connected to the gate of the main IGBT, and the gate thereof is connected to the emitter of the sense IGBT and the cathode of diode. One end of the resistor is connected to the gate of the main IGBT and the source of the MOSFET, and the other end of the resistor is connected to the emitter of the main IGBT and the anode of the diode.

3. 发明授权

US08878239B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08878239B2
公开(公告)日：2014-11-04
申请号：US13886399
申请日：2013-05-03
申请人： Mitsubishi Electric Corporation
发明人： Tomohide Terashima
IPC分类号： H01L29/739 , H01L29/08 , H01L29/06 , H01L29/78 , H01L29/40 , H01L29/10
CPC分类号： H01L29/7393 , H01L29/0657 , H01L29/0692 , H01L29/0696 , H01L29/0834 , H01L29/1087 , H01L29/402 , H01L29/407 , H01L29/7394 , H01L29/7835
摘要： On a main surface of a semiconductor substrate, an N− semiconductor layer is formed with a dielectric portion including relatively thin and thick portions interposed therebetween. In a predetermined region of the N− semiconductor layer, an N-type impurity region and a P-type impurity region are formed. A gate electrode is formed on a surface of a portion of the P-type impurity region located between the N-type impurity region and the N− semiconductor layer. In a predetermined region of the N− semiconductor layer located at a distance from the P-type impurity region, another P-type impurity region is formed. As a depletion layer block portion, another N-type impurity region higher in impurity concentration than the N− semiconductor layer is formed from the surface of the N− semiconductor layer to the dielectric portion.
摘要翻译：在半导体衬底的主表面上，形成具有介于其间相对薄且厚的部分的电介质部分的N-半导体层。在N-半导体层的预定区域中，形成N型杂质区和P型杂质区。在位于N型杂质区域和N-半导体层之间的P型杂质区域的一部分的表面上形成栅电极。在位于距离P型杂质区一定距离的N-半导体层的预定区域中，形成另一P型杂质区。作为耗尽层块部分，从N-半导体层的表面到电介质部分形成杂质浓度高于N-半导体层的另一N型杂质区。

4. 发明授权

US11183386B2 Semiconductor device and method of manufacturing same 有权
公开(公告)号：US11183386B2
公开(公告)日：2021-11-23
申请号：US16587197
申请日：2019-09-30
申请人： Mitsubishi Electric Corporation
发明人： Tomohide Terashima , Yasuhiro Kagawa , Kensuke Taguchi
IPC分类号： H01L21/22 , H01L29/10 , H01L29/16 , H01L29/32 , H01L29/78 , H01L29/66 , H01L29/739
摘要： There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

5. 发明授权

US09048111B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09048111B2
公开(公告)日：2015-06-02
申请号：US14253269
申请日：2014-04-15
申请人： Mitsubishi Electric Corporation
发明人： Junichi Yamashita , Tomohide Terashima
IPC分类号： H01L29/06 , H01L21/762 , H01L27/12
CPC分类号： H01L29/0649 , H01L21/761 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L27/1203
摘要： A semiconductor device includes a substrate, a buried insulating film formed on the substrate, an SOI layer formed on the buried insulating film, an insulating film formed to extend from a top surface of the SOI layer to the buried insulating film and to divide the SOI layer into a first SOI layer and a second SOI layer isolated from the first SOI layer, an element formed in the first SOI layer, and an electrode having at one end thereof a pad located directly above the second SOI layer, the other end of the electrode being connected to the first SOI layer. A cavity region is formed between the buried insulating film and the substrate directly below the first SOI layer. The portion of the buried insulating film directly below the second SOI layer is at least partially in direct contact with the substrate.
摘要翻译：半导体器件包括衬底，在衬底上形成的埋入绝缘膜，形成在掩埋绝缘膜上的SOI层，形成为从SOI层的顶表面延伸到掩埋绝缘膜并将SOI划分的绝缘膜层与第一SOI层隔离的第一SOI层和第二SOI层，形成在第一SOI层中的元件，以及在其一端具有位于第二SOI层正上方的焊盘的另一端电极连接到第一SOI层。在第一SOI层正下方的掩埋绝缘膜和基板之间形成空洞区域。直接在第二SOI层正下方的埋入绝缘膜的部分至少部分地与衬底直接接触。

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