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    • 1. 发明授权
    • Shift register, display device, and electronic device
    • 移位寄存器,显示设备和电子设备
    • US07688107B2
    • 2010-03-30
    • US11387782
    • 2006-03-24
    • Mitsuaki OsameAya AnzaiMizuki Sato
    • Mitsuaki OsameAya AnzaiMizuki Sato
    • H03H11/16
    • G11C19/00G09G3/3674G09G3/3685G11C19/28
    • The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n−1)-th stage operates in accordance with the first output from the previous stage, an output from the second clocked inverter at the previous stage, and the first CK signal; the second clocked inverter at the (2n−1)-th stage operates in accordance with the second output from the previous stage, an output of the first clocked inverter at the (2n−1)-th stage, and the first CK signal; one of the first output and the second output is equal to a potential of VDD and the other is equal to a potential of VSS; the first CK signal at the 2n-th stage operates the third output from the (2n−1)-th stage, an output of the second clocked inverter and the second CK signal; the second clocked inverter at the 2n-th stage operates in accordance with the fourth output from the (2n−1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second CK signal; one of the third output and the fourth output is equal to the potential of VDD and the other is equal to the potential of VSS, and the second CK signal is an inversion signal of the first CK signal and the amplitude of the CK signal is smaller than the power supply potential.
    • 本发明提供一种移位寄存器,其能够有效地操作而不设置电平移位部分。 第(2n-1)级的第一时钟反相器根据前一级的第一输出,前一级的第二时钟反相器的输出和第一CK信号进行工作; (2n-1)级的第二时钟反相器根据前一级的第二输出,第(2n-1)级的第一时钟反相器的输出和第一CK信号进行工作; 第一输出和第二输出之一等于VDD的电位,另一个等于VSS的电位; 第2n级的第一CK信号从第(2n-1)级的第三输出操作第二时钟反相器和第二CK信号的输出; 第2n级的第二时钟反相器根据第(2n-1)级的第四输出,第2n阶段的第一时钟反相器的输出和第二CK信号进行工作; 第三输出和第四输出之一等于VDD的电位,另一个等于VSS的电位,第二个CK信号是第一个CK信号的反相信号,CK信号的幅度较小 比供电潜力大。
    • 2. 发明申请
    • Shift register, display device, and electronic device
    • 移位寄存器,显示设备和电子设备
    • US20060233293A1
    • 2006-10-19
    • US11387782
    • 2006-03-24
    • Mitsuaki OsameAya AnzaiMizuki Sato
    • Mitsuaki OsameAya AnzaiMizuki Sato
    • G11C19/00
    • G11C19/00G09G3/3674G09G3/3685G11C19/28
    • The present invention provides a shift register which can operate favorably without providing a level shift portion. The first clocked inverter at the (2n−1)-th stage operates in accordance with the first output from the previous stage, an output from the second clocked inverter at the previous stage, and the first CK signal; the second clocked inverter at the (2n−1)-th stage operates in accordance with the second output from the previous stage, an output of the first clocked inverter at the (2n−1)-th stage, and the first CK signal; one of the first output and the second output is equal to a potential of VDD and the other is equal to a potential of VSS; the first CK signal at the 2n-th stage operates the third output from the (2n−1)-th stage, an output of the second clocked inverter and the second CK signal; the second clocked inverter at the 2n-th stage operates in accordance with the fourth output from the (2n−1)-th stage, an output from the first clocked inverter at the 2n-th stage, and the second CK signal; one of the third output and the fourth output is equal to the potential of VDD and the other is equal to the potential of VSS, and the second CK signal is an inversion signal of the first CK signal and the amplitude of the CK signal is smaller than the power supply potential.
    • 本发明提供一种移位寄存器,其能够有效地操作而不设置电平移位部分。 第(2n-1)级的第一时钟反相器根据前一级的第一输出,前一级的第二时钟反相器的输出和第一CK信号进行工作; (2n-1)级的第二时钟反相器根据前一级的第二输出,第(2n-1)级的第一时钟反相器的输出和第一CK信号进行工作; 第一输出和第二输出之一等于VDD的电位,另一个等于VSS的电位; 第2n级的第一CK信号从第(2n-1)级的第三输出操作第二时钟反相器和第二CK信号的输出; 第2n级的第二时钟反相器根据第(2n-1)级的第四输出,第2n阶段的第一时钟反相器的输出和第二CK信号进行工作; 第三输出和第四输出之一等于VDD的电位,另一个等于VSS的电位,第二个CK信号是第一个CK信号的反相信号,CK信号的幅度较小 比供电潜力大。
    • 3. 发明授权
    • Shift register and semiconductor display device
    • 移位寄存器和半导体显示器件
    • US08664976B2
    • 2014-03-04
    • US13248420
    • 2011-09-29
    • Mitsuaki OsameAya Anzai
    • Mitsuaki OsameAya Anzai
    • G09G3/36G11C19/00G06F7/38
    • G09G3/3677G09G3/3266G09G3/3275G09G3/3688G11C19/00G11C19/28
    • The invention provides a shift register which can operate normally while suppressing a delay of signal and a rounding of waveform. The shift register of the invention includes a plurality of stages of flip-flop circuits each of which includes a clocked inverter. The clocked inverter includes a first transistor and a second transistor which are connected in series, a first compensation circuit including a third transistor and a fourth transistor which are connected in series, and a second compensation circuit including a fifth transistor and a transmission gate. According to the first compensation circuit, a timing at which a signal outputted from the flip-flop circuit rises or falls can be controlled in synchronization with an output of two stages before. The second compensation circuit can control a clock signal input can be controlled.
    • 本发明提供了一种能够在抑制信号延迟和波形舍入的同时正常工作的移位寄存器。 本发明的移位寄存器包括多个级的触发器电路,每个触发器电路包括时钟反相器。 时钟反相器包括串联连接的第一晶体管和第二晶体管,包括串联连接的第三晶体管和第四晶体管的第一补偿电路和包括第五晶体管和透射栅的第二补偿电路。 根据第一补偿电路,可以与前两级的输出同步地控制从触发器电路输出的信号上升或下降的定时。 第二补偿电路可以控制时钟信号输入可以控制。