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1. 发明授权

US07983889B2 Simulation method and simulation apparatus for LDMOSFET 失效
标题翻译： LDMOSFET的仿真方法和仿真装置
公开(公告)号：US07983889B2
公开(公告)日：2011-07-19
申请号：US12130320
申请日：2008-05-30
申请人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
发明人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
摘要翻译：用于增加LDMOSFET中的击穿电压的漂移区域被认为是电阻元件。通过迭代计算考虑电阻的电位分布来计算整个装置的电位分布。假设线性电位分布，分析地计算在漂移区域中产生的电容。通过考虑从耗尽区域到累积区域的电位来计算在栅电极和漂移区域之间的重叠区域中产生的电容。

2. 发明申请

US20090070084A1 SIMULATION METHOD AND SIMULATION APPARATUS FOR LDMOSFET 失效
标题翻译： LDMOSFET的仿真方法和仿真设备
公开(公告)号：US20090070084A1
公开(公告)日：2009-03-12
申请号：US12130320
申请日：2008-05-30
申请人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
发明人： Mitiko Miura , Masahiro Yokomichi , Takahiro Kajiwara , Norio Sadachika , Masataka Miyake , Takahiro Iizuka , Masahiko Taguchi , Tatsuya Ohguro
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： The drift region for increasing the breakdown voltage in an LDMOSFET is regarded as a resistive element. The potential distribution of the overall device is calculated by obtaining a potential distribution considering the resistance by iterative calculation. A capacitance generated in the drift region is analytically calculated assuming a linear potential distribution. A capacitance generated in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.
摘要翻译：用于增加LDMOSFET中的击穿电压的漂移区域被认为是电阻元件。通过迭代计算考虑电阻的电位分布来计算整个装置的电位分布。假设线性电位分布，分析地计算在漂移区域中产生的电容。通过考虑从耗尽区域到累积区域的电位来计算在栅电极和漂移区域之间的重叠区域中产生的电容。

3. 发明授权

US08731893B2 Circuit simulation of MOSFETs 有权
标题翻译： MOSFET的电路仿真
公开(公告)号：US08731893B2
公开(公告)日：2014-05-20
申请号：US13080154
申请日：2011-04-05
申请人： Mitiko Miura-Mattausch , Norio Sadachika , Shunta Kusu , Takaki Yoshida
发明人： Mitiko Miura-Mattausch , Norio Sadachika , Shunta Kusu , Takaki Yoshida
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
摘要翻译：算术装置通过基于存储在存储装置中的数学表达式和装置参数进行计算来计算硅层的表面电位。同样，当硅层处于部分耗尽状态时，当硅处于完全耗尽状态时，算术装置计算掩埋氧化膜下的体层的表面电位。然后，运算装置根据计算出的硅层的表面电位，体积层的计算出的表面电位，存储在存储装置中的数学式进行计算，通过迭代计算得到体层的表面电位。算术装置根据通过迭代计算获得的体层的表面电位和存储在存储装置中的数学表达式进行计算，并计算硅层的下表面电位。

4. 发明申请

US20110184708A1 SIMULATION METHOD AND SIMULATION APPARATUS 有权
标题翻译：模拟方法和仿真设备
公开(公告)号：US20110184708A1
公开(公告)日：2011-07-28
申请号：US13080154
申请日：2011-04-05
申请人： Mitiko MIURA-MATTAUSCH , Norio Sadachika , Shunta Kusu , Takaki Yoshida
发明人： Mitiko MIURA-MATTAUSCH , Norio Sadachika , Shunta Kusu , Takaki Yoshida
IPC分类号： G06F17/50 , G06F7/60
CPC分类号： G06F17/5036
摘要： An arithmetic device calculates the surface potential of a silicon layer by performing computation based on a mathematical expression and device parameters stored in a storage device. Likewise, the arithmetic device calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in a partially depleted state and when the silicon is in a fully depleted state. The arithmetic device then performs computation based on the calculated surface potential of the silicon layer, the calculated surface potential of the bulk layer, and mathematical expressions stored in the storage device, and obtains the surface potential of the bulk layer by, iterative calculation. The arithmetic device performs computation based on the surface potential of the bulk layer obtained by iterative calculation and mathematical expressions stored in the storage device, and calculates the lower surface potential of the silicon layer.
摘要翻译：算术装置通过基于存储在存储装置中的数学表达式和装置参数进行计算来计算硅层的表面电位。同样，当硅层处于部分耗尽状态时，当硅处于完全耗尽状态时，算术装置计算掩埋氧化膜下的体层的表面电位。运算装置然后根据计算出的硅层表面电位，体积层的计算出的表面电位和存储在存储装置中的数学式进行计算，并通过迭代计算得到体层的表面电位。算术装置根据通过迭代计算获得的体层的表面电位和存储在存储装置中的数学表达式进行计算，并计算硅层的下表面电位。

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