专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5781682A Low-cost packaging for parallel optical computer link 失效
标题翻译：并行光计算机连接的低成本封装
公开(公告)号：US5781682A
公开(公告)日：1998-07-14
申请号：US595149
申请日：1996-02-01
申请人： Mitchell Simmons Cohen , Marco Gauvin , Glen Walden Johnson , Daniel M. Kuchta , Andre Lacerte , Nicholas Anthony Lee , Sylvain Ouimet , Stephen Louis Spanoudis , Stephane Tremblay , Jeannine Madelyn Trewhella
发明人： Mitchell Simmons Cohen , Marco Gauvin , Glen Walden Johnson , Daniel M. Kuchta , Andre Lacerte , Nicholas Anthony Lee , Sylvain Ouimet , Stephen Louis Spanoudis , Stephane Tremblay , Jeannine Madelyn Trewhella
IPC分类号： G02B6/38 , G02B6/42 , H01L21/02 , H01L21/8242 , G02B6/00 , G02B6/36
CPC分类号： G02B6/4292 , G02B6/4249 , G02B6/4255 , G02B6/4261 , G02B6/4272 , G02B6/4274 , G02B6/4277 , G02B6/4284 , H01L27/10852 , H01L28/84 , G02B6/3893 , G02B6/4245 , G02B6/4283 , H01L2924/0002
摘要： Parallel optical coupling apparatus for coupling a connector attached to one end of a parallel optical cable to a receiver or transmitter array. A parallel fiber optic assembly includes a receiver or transmitter array subassembly that houses a parallel optical coupler for transferring optical signals from an array of sources (e.g., lasers) in the assembly to the connector, or from the connector to an array of receiving elements in the assembly. A connector shell is provided that properly aligns the connector with respect to the optical coupler array.
摘要翻译：用于将连接到并行光缆的一端的连接器耦合到接收器或发射器阵列的并行光耦合装置。并联光纤组件包括接收器或发射器阵列子组件，其容纳用于将光信号从组件中的源阵列（例如，激光器）传送到连接器或从连接器到接收元件阵列的并行光耦合器大会。提供连接器壳体，其使连接器相对于光耦合器阵列正确对准。

2. 发明授权

US6137158A Leadframe and leadframe assembly for parallel optical computer link 失效
标题翻译：用于并行光学计算机链接的引线框和引线框组件
公开(公告)号：US6137158A
公开(公告)日：2000-10-24
申请号：US88064
申请日：1998-06-01
申请人： Mitchell Simmons Cohen , Marco Gauvin , Glen Walden Johnson , Daniel M. Kuchta , Andre Lacerte , Nicholas Anthony Lee , Sylvain Ouimet , Stephen Louis Spanoudis , Stephane Tremblay , Jeannine Madelyn Trewhella
发明人： Mitchell Simmons Cohen , Marco Gauvin , Glen Walden Johnson , Daniel M. Kuchta , Andre Lacerte , Nicholas Anthony Lee , Sylvain Ouimet , Stephen Louis Spanoudis , Stephane Tremblay , Jeannine Madelyn Trewhella
IPC分类号： G02B6/38 , G02B6/42 , H01L21/02 , H01L21/8242 , H01L23/48 , G02B6/00 , G32B6/36
CPC分类号： G02B6/4292 , G02B6/4249 , G02B6/4255 , G02B6/4261 , G02B6/4272 , G02B6/4274 , G02B6/4277 , G02B6/4284 , H01L27/10852 , H01L28/84 , G02B6/3893 , G02B6/4245 , G02B6/4283 , H01L2924/0002
摘要： Parallel optical coupling apparatus for coupling a connector attached to one end of a parallel optical cable to a receiver or transmitter array. A parallel fiber optic assembly includes a receiver or transmitter array subassembly that houses a parallel optical coupler for transferring optical signals from an array of sources (e.g., lasers) in the assembly to the connector, or from the connector to an array of receiving elements in the assembly. A connector shell is provided that properly aligns the connector with respect to the optical coupler array.
摘要翻译：用于将连接到并行光缆的一端的连接器耦合到接收器或发射器阵列的并行光耦合装置。并联光纤组件包括接收器或发射器阵列子组件，其容纳用于将光信号从组件中的源阵列（例如，激光器）传送到连接器或从连接器到接收元件阵列的并行光耦合器大会。提供连接器壳体，其使连接器相对于光耦合器阵列正确对准。

3. 发明授权

US06798953B1 Guides lithographically fabricated on semiconductor devices 有权
标题翻译：在半导体器件上光刻制造的引导线
公开(公告)号：US06798953B1
公开(公告)日：2004-09-28
申请号：US09479109
申请日：2000-01-07
申请人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
发明人： Mitchell S. Cohen , Michael J. Cordes , Steven A. Cordes , William K. Hogan , Glen W. Johnson , Daniel M. Kuchta , Dianne L. Lacey , James L. Speidell , Jeannine M. Trewhella , Joseph P. Zinter
IPC分类号： G02B630
CPC分类号： G02B6/4246 , G02B6/3652 , G02B6/423 , G02B6/4239
摘要： A structure that includes a substrate, typically a semiconductor chip such as a VCSEL or photodetector chip, and a guide for aligning a signal conveying device, typically an optical fiber, to a transducer such as an optoelectronic device on the semiconductor chip. The guide is formed, in a preferred embodiment, by lithographically exposing and developing a thick layer of photoresist. The structure is assembled by placing and securing the signal conveying device into a cavity-like region of the guide.
摘要翻译：包括基板，通常为诸如VCSEL或光电检测器芯片的半导体芯片的结构，以及用于将信号传送装置（通常为光纤）对准到诸如半导体芯片上的光电子装置的换能器的引导件。在优选实施例中，通过光刻曝光和显影厚的光致抗蚀剂层来形成引导件。通过将信号传送装置放置并固定到引导件的腔状区域来组装结构。

4. 发明授权

US06273400B1 Semiconductor wafer testing structure 失效
标题翻译：半导体晶圆测试结构
公开(公告)号：US06273400B1
公开(公告)日：2001-08-14
申请号：US09037675
申请日：1998-03-10
申请人： Daniel M. Kuchta
发明人： Daniel M. Kuchta
IPC分类号： H01L2358
CPC分类号： H01S5/0261 , G01R31/2822 , G01R31/2831 , G01R31/2884 , G01R31/316 , H01S5/0042 , H01S5/0201 , H01S5/0422 , H01S5/0428 , H01S5/183
摘要： The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the devices performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
摘要翻译：本发明是减少用于测试包含在半导体晶片内的电气装置的AC测试信号路径的电感的结构和方法。这扩大了测试的频率范围。它能够在比其他可用的频率更高的频率下测试设备性能特性。它特别针对测试晶圆上的VCSEL。该方法向电气设备提供了微波偏置三通装置的特性。晶片电容器设计在电气设备的环境中，能够形成和使用偏置三通的三个端口。优选地，偏置三通以不需要向晶片制造过程添加处理步骤的方式形成。该方法还提供了增加晶圆上电容器的电容的方法。

5. 发明授权

US5891746A Semiconductor wafer testing method and apparatus 失效
标题翻译：半导体晶圆测试方法和装置
公开(公告)号：US5891746A
公开(公告)日：1999-04-06
申请号：US37466
申请日：1998-03-10
申请人： Daniel M. Kuchta
发明人： Daniel M. Kuchta
IPC分类号： G01R31/28 , G01R31/316 , H01S5/00 , H01S5/02 , H01S5/042 , H01S5/183 , H01S3/103
CPC分类号： H01S5/0042 , G01R31/2822 , G01R31/2831 , G01R31/2884 , G01R31/316 , H01S5/0201 , H01S5/0261 , H01S5/0422 , H01S5/183
摘要： The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.
摘要翻译：本发明是减少用于测试包含在半导体晶片内的电气装置的AC测试信号路径的电感的结构和方法。这扩大了测试的频率范围。它能够以比其他可用的更高的频率测试设备的性能特征。它特别针对测试晶圆上的VCSEL。该方法向电气设备提供了微波偏置三通装置的特性。晶片电容器设计在电气设备的环境中，能够形成和使用偏置三通的三个端口。优选地，偏置三通以不需要向晶片制造过程添加处理步骤的方式形成。该方法还提供了增加晶圆上电容器的电容的方法。

6. 发明授权

US5757027A Semiconductor wafer testing method and apparatus 失效
公开(公告)号：US5757027A
公开(公告)日：1998-05-26
申请号：US588467
申请日：1996-01-16
申请人： Daniel M. Kuchta
发明人： Daniel M. Kuchta
IPC分类号： G01R31/28 , G01R31/316 , H01S5/00 , H01S5/02 , H01S5/026 , H01S5/042 , H01S5/183 , H01L23/58 , H01S3/19
CPC分类号： H01S5/0261 , G01R31/2822 , G01R31/2831 , G01R31/2884 , H01S5/0042 , G01R31/316 , H01S5/0201 , H01S5/0422 , H01S5/0428 , H01S5/183
摘要： The present invention is a structure and method to reduce the inductance of the AC test signal path used for testing an electrical device contained within a semiconductor wafer. This extends the frequency range of testing. It enables testing the device's performance characteristics at higher frequencies than otherwise useable. It is particularly directed for testing on-wafer VCSELs. The method provides to the electrical device the characteristics of a microwave bias-tee device. An on wafer capacitor is designed into the environment of the electrical device enabling the formation and use of the three ports of a bias-tee. Preferably, the bias-tee is formed in a manner not requiring the addition of processing steps to the wafer manufacturing process. The method further provides a way to increase the capacitance of the on-wafer capacitor.

7. 发明申请

US20130151812A1 NODE INTERCONNECT ARCHITECTURE TO IMPLEMENT HIGH-PERFORMANCE SUPERCOMPUTER 有权
标题翻译：节点互连结构实现高性能超级计算机
公开(公告)号：US20130151812A1
公开(公告)日：2013-06-13
申请号：US13313145
申请日：2011-12-07
申请人： Evan G. Colgan , Monty M. Denneau , Daniel M. Kuchta
发明人： Evan G. Colgan , Monty M. Denneau , Daniel M. Kuchta
IPC分类号： G06F15/76 , G06F9/02
CPC分类号： H04B10/40 , G06F15/161 , G06F15/163 , G06F15/173 , G06F15/17337 , H04B10/2503 , H04L5/14
摘要： Node Interconnect architectures to implement a high performance supercomputer are provided. For example, a node interconnect architecture for connecting a multitude of nodes (or processors) of a supercomputer is implemented using an all-to-all electrical and optical connection network which provides two independent communication paths between any two processors of the supercomputer, wherein a communication path includes at most two electrical links and one optical link.
摘要翻译：提供节点互连架构来实现高性能超级计算机。例如，用于连接超级计算机的多个节点（或处理器）的节点互连体系架构是使用提供超级计算机的任何两个处理器之间的两个独立通信路径的全对电连接网络来实现的，其中a 通信路径最多包括两个电连接和一个光链路。

8. 发明授权

US07885540B2 Methods and apparatus for optical modulation amplitude measurement 失效
标题翻译：用于光调制幅度测量的方法和装置
公开(公告)号：US07885540B2
公开(公告)日：2011-02-08
申请号：US12114374
申请日：2008-05-02
申请人： Casimer DeCusatis , Daniel M. Kuchta , Jeremy Daniel Schaub
发明人： Casimer DeCusatis , Daniel M. Kuchta , Jeremy Daniel Schaub
IPC分类号： H04B10/08 , G01M11/00
CPC分类号： G01M11/333 , G01M11/30
摘要： Techniques for measuring optical modulation amplitude (OMA) are disclosed. For example, a technique for measuring an OMA value associated with an input signal includes the following steps/operations. The input signal is applied to a photodetector, wherein the photodetector is calibrated to have a given responsivity value R, and further wherein the photodetector generates an output signal in response to the input signal. The output signal from the photodetector is applied to a radio frequency (RF) power meter, wherein the RF power meter measures the root mean squared (RMS) power value of the output signal received from the photodetector. The OMA value associated with the input signal is determined in response to the root mean squared (RMS) power value measured by the RF power meter. The OMA value may be determined as a function of a factor F derived from a relationship between an amplitude of a data signal and the RMS value of the data signal.
摘要翻译：公开了用于测量光调制幅度（OMA）的技术。例如，用于测量与输入信号相关联的OMA值的技术包括以下步骤/操作。输入信号被施加到光电检测器，其中光电检测器被校准为具有给定的响应值R，并且其中光电检测器响应于输入信号产生输出信号。来自光电检测器的输出信号被施加到射频（RF）功率计，其中RF功率计测量从光电检测器接收的输出信号的均方根（RMS）功率值。响应于由RF功率计测得的均方根（RMS）功率值，确定与输入信号相关的OMA值。可以根据数据信号的幅度与数据信号的RMS值之间的关系导出的因子F的函数来确定OMA值。

9. 发明授权

US07062121B2 Method and apparatus for a scalable parallel computer based on optical fiber broadcast 有权
标题翻译：基于光纤广播的可扩展并行计算机的方法和装置
公开(公告)号：US07062121B2
公开(公告)日：2006-06-13
申请号：US10295255
申请日：2002-11-15
申请人： Blake G. Fitch , Robert S. Germain , Glen W. Johnson , Daniel M. Kuchta , Jeannine M. Trewhella
发明人： Blake G. Fitch , Robert S. Germain , Glen W. Johnson , Daniel M. Kuchta , Jeannine M. Trewhella
IPC分类号： G02B6/28
CPC分类号： G06E1/00
摘要： An information processing system, includes several processors, each having at least one optical fiber input and at least one optical fiber output; a controller having an optical fiber input and at least one fiber output; fibers, bundled for transmitting information; and a fiber bundle redriver, coupled to the controller, having an input channel and an output channel, for simultaneously redriving an optical signal received from any selected one of the plurality of input fibers onto substantially all of the plurality of output fibers. The fiber output of each of the plurality of processors and the at least one fiber output of the controller are respectively is coupled to the input channel of the fiber bundle redriver, and the at least one fiber input of each of said plurality of processors and the fiber input of the controller are respectively coupled to the output channel of the fiber bundle redriver.
摘要翻译：信息处理系统包括几个处理器，每个处理器具有至少一个光纤输入和至少一个光纤输出; 具有光纤输入和至少一个光纤输出的控制器; 捆绑的光纤，用于传输信息; 以及耦合到所述控制器的具有输入通道和输出通道的光纤束驱动器，用于同时将从所述多个输入光纤中的任何选定的输入光纤接收的光信号重新分配到基本上所有多个输出光纤上。多个处理器中的每一个的光纤输出和控制器的至少一个光纤输出分别耦合到光纤束转接器的输入通道，并且所述多个处理器中的每一个的至少一个光纤输入和控制器的光纤输入分别耦合到光纤束转接器的输出通道。

10. 发明授权

US6111430A Circuit for interfacing a first type of logic circuit with a second type of logic circuit 失效
标题翻译：用于将第一类逻辑电路与第二类逻辑电路接口的电路
公开(公告)号：US6111430A
公开(公告)日：2000-08-29
申请号：US104602
申请日：1998-06-24
申请人： Daniel M. Kuchta , Jungwook Yang
发明人： Daniel M. Kuchta , Jungwook Yang
IPC分类号： H03K19/0185 , H03K19/0175 , H03K19/094 , H03K19/20
CPC分类号： H03K19/018535
摘要： A circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises a depletion mode MESFET device, coupled between at least one CMOS device and at least one other MESFET device, the depletion mode MESFET device limiting a current through a gate-source junction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of the at least one other MESFET device. Another circuit for interfacing CMOS logic devices, having an output level range associated therewith, with MESFET logic devices, having an input level range associated therewith, comprises: a source follower MESFET device coupled to an output terminal of at least one CMOS device; a first depletion mode MESFET device, coupled to the source follower MESFET device, the first depletion mode MESFET device limiting a current through a gate-source juction thereof such that the output level range of the at least one CMOS device is altered to be compatible with the input level range of at least one other MESFET device; and a second depletion mode MESFET device, coupled to the first depletion mode MESFET device, for providing a discharge path; wherein an input terminal of the at least one other MESFET device is coupled between the first and second depletion mode MESFET devices.
摘要翻译：用于与具有与其相关联的输入电平范围的MESFET逻辑器件具有与其相关联的具有输出电平范围的CMOS逻辑器件的电路包括耗尽型MESFET器件，耦合在至少一个CMOS器件与至少一个其它MESFET器件耗尽型MESFET器件限制通过栅极 - 源极结的电流，使得至少一个CMOS器件的输出电平范围被改变为与至少一个其它MESFET器件的输入电平范围兼容。用于与具有与其相关联的输入电平范围的具有MESFET逻辑器件的具有与其相关联的输出电平范围的CMOS逻辑器件的接口的另一电路包括：耦合到至少一个CMOS器件的输出端的源极跟随器MESFET器件; 耦合到源极跟随器MESFET器件的第一耗尽型MESFET器件，第一耗尽型MESFET器件限制通过栅极源极漏极的电流，使得至少一个CMOS器件的输出电平范围被改变为与至少一个其它MESFET器件的输入电平范围; 以及耦合到所述第一耗尽型MESFET器件的用于提供放电路径的第二耗尽型MESFET器件; 其中所述至少一个其它MESFET器件的输入端耦合在所述第一和第二耗尽型MESFET器件之间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式