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    • 2. 发明授权
    • Information processing system, information compression device, information decompression device, information processing method, and program
    • 信息处理系统,信息压缩装置,信息解压装置,信息处理方法和程序
    • US09553604B2
    • 2017-01-24
    • US13262181
    • 2010-03-19
    • Hiroaki Inoue
    • Hiroaki Inoue
    • H03M7/30G11C7/10H04L29/12G11C29/00
    • H03M7/30G11C7/103G11C29/003H04L29/12311
    • In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and outputting the result as compressed configuration information.
    • 为了在发送或存储具有不同特征的地址和数据的配置信息的情况下提高包括地址信息和数据信息的配置信息的压缩率,信息压缩装置设置有作为输入接收并压缩提供的配置信息的压缩器 具有地址和数据的压缩信息存储模块,以及用于将被压缩的配置信息(即,压缩配置信息)存储为要为用户解压缩的信息的压缩信息存储模块,所述压缩器包括用于分离配置信息的信息分离模块 地址信息和数据信息,分离地压缩分离的地址信息和数据信息的地址压缩器和数据压缩器,以及压缩信息输出模块,用于将压缩的地址信息和数据 信息并将结果作为压缩配置信息输出。
    • 3. 发明授权
    • Semiconductor integrated circuit device, method of controlling semiconductor integrated circuit device, and cache device
    • 半导体集成电路器件,半导体集成电路器件的控制方法及缓存器件
    • US09164905B2
    • 2015-10-20
    • US13393814
    • 2010-08-18
    • Hiroaki Inoue
    • Hiroaki Inoue
    • G06F12/00G06F12/08
    • G06F12/0802G06F2212/1028Y02D10/13
    • There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).
    • 提供了一种半导体集成电路器件,一种半导体集成电路器件的控制方法和能够有效地实现功率节省的高速缓存器件,其中该高速缓存器件包括一个使能高速缓存(200)的低压工作, 区域缓存(300)具有与高速缓存(200)不同的类型,高速缓存(200)和高速缓存(300)被独立地提供源电压; 高速缓存(200)可操作在低于高速缓存(300)可操作的下限电压的电压; 高速缓存控制单元(400)在允许仅高速缓存(200)操作的第一模式和允许高速缓存(200)或高速缓存(300)操作的第二模式之间操作可切换控制; 以及在所述第一模式下的所述高速缓存(200)工作以提供低于所述高速缓存(300)可操作的所述下限电压的电压,同时中断向所述高速缓存(300)的电力供应。
    • 6. 发明授权
    • Information processing apparatus, execution environment transferring method and program thereof
    • 信息处理装置,执行环境转移方法及程序
    • US08473702B2
    • 2013-06-25
    • US12602871
    • 2008-06-05
    • Hiroaki InoueTsuyoshi AbeJunji SakaiMasato Edahiro
    • Hiroaki InoueTsuyoshi AbeJunji SakaiMasato Edahiro
    • G06F12/00
    • G06F9/44505G06F9/4856
    • Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.
    • 提供一种能够在短时间内传送执行环境而不降低执行环境的基本性能而不需要大量存储器的信息处理装置。 信息处理装置包括用于执行基本处理的基本侧CPU 100和用于执行附加处理的附加侧CPU200,其中设置在基本侧CPU 100上的传送管理单元300传送包括执行的结构信息的执行环境数据1000 在附加侧CPU执行的附加处理的环境30和与执行环境相对应的存储器中的数据到其他信息处理装置,并且基于接收到的执行环境数据1000恢复执行环境以重新启动加法侧CPU 。
    • 7. 发明申请
    • MANUFACTURING METHOD OF MEMS DEVICE, AND SUBSTRATE USED THEREFOR
    • MEMS器件的制造方法及其使用的衬底
    • US20130022790A1
    • 2013-01-24
    • US13609703
    • 2012-09-11
    • Hiroaki InoueTadashi NakataniSatoshi Ueda
    • Hiroaki InoueTadashi NakataniSatoshi Ueda
    • B32B3/30
    • H01H59/0009Y10T428/24521Y10T428/24562
    • A method for manufacturing a MEMS device, includes: preparing a substrate provided with a first substrate in which a cavity is formed, and a second substrate that is bonded to a side of the first substrate and includes a slit to delimit a movable portion in a position corresponding to the cavity, the second substrate, including a first surface thereof facing the first substrate, being provided with a thermally-oxidized film selectively formed on the first surface in a position corresponding to the movable portion; forming a first electrode layer on a second surface opposite to the first surface; forming a sacrifice lager on the first electrode layer and the second substrate; forming a second electrode layer on the sacrifice layer; and removing the sacrifice layer and the thermally-oxidized film after the second electrode layer is formed.
    • 一种MEMS器件的制造方法,其特征在于,包括:准备具有形成有空腔的第一基板的基板和与所述第一基板的一侧接合的第二基板,所述第二基板包括用于限定所述第一基板的可动部的狭缝 包括与第一基板相对的第一表面的第二基板设置有在与第一基板相对应的位置上选择性地形成在第一表面上的热氧化膜; 在与所述第一表面相对的第二表面上形成第一电极层; 在所述第一电极层和所述第二基板上形成牺牲物; 在牺牲层上形成第二电极层; 并且在形成第二电极层之后去除牺牲层和热氧化膜。