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1. 发明授权

US08183920B2 Variable gain amplifier with reduced power consumption 有权
标题翻译：可变增益放大器，功耗降低
公开(公告)号：US08183920B2
公开(公告)日：2012-05-22
申请号：US12828238
申请日：2010-06-30
申请人： Jieming Qi , David W. Boerstler , Minhan Chen , Hayden C. Cranford, Jr.
发明人： Jieming Qi , David W. Boerstler , Minhan Chen , Hayden C. Cranford, Jr.
IPC分类号： H03F3/45
CPC分类号： H03G3/004 , H03F1/0205 , H03F3/189 , H03F3/45632 , H03F2200/294 , H03F2200/555 , H03F2203/45418
摘要： A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.
摘要翻译：可变增益放大器包括被配置为接收一对差分信号的第一差分信号的第一共模（CM）节点。第一调节器耦合到第一CM节点，第一调节器被配置为生成第一CM偏移。第二CM节点被配置为接收该对差分信号的第二差分信号。第二调节器耦合到第二CM节点，第二调节器被配置为生成第二CM偏移。在一个实施例中，第一CM偏移和第二CM偏移量一起包括净CM偏移，净CM偏移被配置为替换当前源净偏移。

2. 发明申请

US20130064326A1 SERIAL LINK RECEIVER FOR HANDLING HIGH SPEED TRANSMISSIONS 有权
标题翻译：串行接收器用于处理高速传输
公开(公告)号：US20130064326A1
公开(公告)日：2013-03-14
申请号：US13228512
申请日：2011-09-09
申请人： Minhan Chen , Hayden C. Cranford, JR.
发明人： Minhan Chen , Hayden C. Cranford, JR.
IPC分类号： H04L27/00
CPC分类号： H04L25/0276 , H04L25/0298
摘要： A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.
摘要翻译：串行链路接收机包括用于接收串行数据信号的正和负输入的第一和第二输入端，耦合到第一和第二输入端的第一和第二宽带匹配T型线圈，耦合到第一和第二AC / DC耦合网络第一和第二宽带匹配T型线圈，以及耦合到来自第一和第二AC / DC耦合网络的输出的共模电平移位器。该接收机架构结合了具有宽带宽输入和通过低频和高频数据信号的能力。该AC和DC耦合前端还结合了共模电平转换网络的特征，以将信号的共模放置在第一有源放大器级的最佳点。

3. 发明授权

US06535043B2 Clock signal selection system, method of generating a clock signal and programmable clock manager including same 有权
标题翻译：时钟信号选择系统，产生时钟信号的方法和包括其的可编程时钟管理器
公开(公告)号：US06535043B2
公开(公告)日：2003-03-18
申请号：US09863656
申请日：2001-05-23
申请人： Minhan Chen
发明人： Minhan Chen
IPC分类号： H03K300
CPC分类号： G06F1/10 , H03K5/13 , H03K5/133 , H03K19/017581 , H03K19/17732 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17748 , H03K19/1776 , H03K19/17788 , H03K19/17792 , H03L7/081 , H03L7/0996
摘要： For use with a programmable clock manager (PCM), a selection system and method of generating a clock signal. In one embodiment, the selection system includes a phase selector, having multiple taps, configured to generate multiple phase shifted signals from a reference signal corresponding to an input signal with a fixed phase shift therebetween. The phase selector is further configured to select at least two of the phase shifted signals. The selection system further includes a duty cycle synthesis circuit configured to generate a clock signal having a duty cycle as a function of a phase shift between the selected phase shifted signals.
摘要翻译：用于可编程时钟管理器（PCM），选择系统和产生时钟信号的方法。在一个实施例中，选择系统包括具有多个抽头的相位选择器，其被配置为从对应于其间具有固定相移的输入信号的参考信号产生多个相移信号。相位选择器还被配置为选择至少两个相移信号。所述选择系统还包括占空比合成电路，其被配置为产生具有作为所选择的相移信号之间的相移的函数的占空比的时钟信号。

4. 发明授权

US08798204B2 Serial link receiver for handling high speed transmissions 有权
标题翻译：用于处理高速传输的串行链路接收器
公开(公告)号：US08798204B2
公开(公告)日：2014-08-05
申请号：US13228512
申请日：2011-09-09
申请人： Minhan Chen , Hayden C. Cranford, Jr.
发明人： Minhan Chen , Hayden C. Cranford, Jr.
IPC分类号： H03K9/00 , H04B3/00
CPC分类号： H04L25/0276 , H04L25/0298
摘要： A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.
摘要翻译：串行链路接收机包括用于接收串行数据信号的正和负输入的第一和第二输入端，耦合到第一和第二输入端的第一和第二宽带匹配T型线圈，耦合到第一和第二AC / DC耦合网络第一和第二宽带匹配T型线圈，以及耦合到来自第一和第二AC / DC耦合网络的输出的共模电平移位器。该接收机架构结合了具有宽带宽输入和通过低频和高频数据信号的能力。该AC和DC耦合前端还结合了共模电平转换网络的特征，以将信号的共模放置在第一有源放大器级的最佳点。

5. 发明申请

US20120001691A1 VARIABLE GAIN AMPLIFIER WITH REDUCED POWER CONSUMPTION 有权
标题翻译：具有降低功耗的可变增益放大器
公开(公告)号：US20120001691A1
公开(公告)日：2012-01-05
申请号：US12828238
申请日：2010-06-30
申请人： Jieming Qi , David W. Boerstler , Minhan Chen , Hayden C. Cranford, JR.
发明人： Jieming Qi , David W. Boerstler , Minhan Chen , Hayden C. Cranford, JR.
IPC分类号： H03F3/45
CPC分类号： H03G3/004 , H03F1/0205 , H03F3/189 , H03F3/45632 , H03F2200/294 , H03F2200/555 , H03F2203/45418
摘要： A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.
摘要翻译：可变增益放大器包括被配置为接收一对差分信号的第一差分信号的第一共模（CM）节点。第一调节器耦合到第一CM节点，第一调节器被配置为生成第一CM偏移。第二CM节点被配置为接收该对差分信号的第二差分信号。第二调节器耦合到第二CM节点，第二调节器被配置为生成第二CM偏移。在一个实施例中，第一CM偏移和第二CM偏移量一起包括净CM偏移，净CM偏移被配置为替换当前源净偏移。

6. 发明申请

US20070035342A1 Differential amplifier offset voltage minimization independently from common mode voltage adjustment 失效
公开(公告)号：US20070035342A1
公开(公告)日：2007-02-15
申请号：US11203860
申请日：2005-08-15
申请人： Minhan Chen , Westerfield Ficken , Louis Hsu , Steven Zier
发明人： Minhan Chen , Westerfield Ficken , Louis Hsu , Steven Zier
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F2203/45424 , H03F2203/45431 , H03F2203/45488 , H03F2203/45646
摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.

7. 发明申请

US20090146722A1 Systems and Arrangements to Provide Input Offset Voltage Compensation 审中-公开
标题翻译：提供输入失调电压补偿的系统和布置
公开(公告)号：US20090146722A1
公开(公告)日：2009-06-11
申请号：US11953346
申请日：2007-12-10
申请人： Minhan Chen , Hayden C. Cranford, Jr. , Bobak Modaress-Razavi
发明人： Minhan Chen , Hayden C. Cranford, Jr. , Bobak Modaress-Razavi
IPC分类号： H03L5/00 , H04L7/00
CPC分类号： H03F3/45183 , H03F3/45744 , H03F2203/45652 , H03F2203/45681
摘要： In one embodiment a method is disclosed that includes applying a series of voltages to an input of an offset evaluation latch, detecting an offset voltage from the offset evaluation latch in response to the application of the series of voltages, and applying an offset compensation voltage to the input of a plurality of sampling latch in response to the detected offset voltage. In some embodiments a digital value can be assigned to the applied offset voltage. When the offset voltage is determined, it can be applied to a plurality sampling latches and a data stream can be received and clock and data recovery can be performed.
摘要翻译：在一个实施例中，公开了一种方法，其包括将一系列电压施加到偏移评估锁存器的输入端，响应于所述一系列电压的应用来检测来自所述偏移评估锁存器的偏移电压，以及将偏移补偿电压施加到响应于检测到的偏移电压而输入多个采样锁存器。在一些实施例中，可以将数字值分配给所施加的偏移电压。当确定偏移电压时，可以将其应用于多个采样锁存器，并且可以接收数据流，并且可以执行时钟和数据恢复。

8. 发明授权

US07486114B2 Signal detector with calibration circuit arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US07486114B2
公开(公告)日：2009-02-03
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： H03K5/19
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method to detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：一种用于检测输入差分信号的存在或不存在的信号检测器和方法。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

9. 发明申请

US20070271054A1 Signal Detector with Calibration Circuit Arrangement 有权
标题翻译：具有校准电路布置的信号检测器
公开(公告)号：US20070271054A1
公开(公告)日：2007-11-22
申请号：US11383821
申请日：2006-05-17
申请人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
发明人： Minhan Chen , Louis Hsu , Joseph Natonio , Karl D. Selander , Michael A. Sorna , Steven J. Zier
IPC分类号： G06F19/00
CPC分类号： H04L25/0274 , H04L25/0296
摘要： A signal detector and method detect the presence or absence of an incoming differential signal. The method nullifies the DC off-set of the signal detector so that it can detect a signal within a very narrow window. The common mode levels of the signal and reference paths are used for calibration which is done automatically by use of an embedded algorithm residing in a digital block. The calibration range and resolution are predetermined to cope with the technology, modeling, design methodology and human error.
摘要翻译：信号检测器和方法检测输入差分信号的存在或不存在。该方法使信号检测器的DC偏移无效，使得其可以在非常窄的窗口内检测信号。信号和参考路径的共模电平用于通过使用位于数字块中的嵌入式算法自动完成的校准。预定校准范围和分辨率，以应对技术，建模，设计方法和人为错误。

10. 发明授权

US07268624B2 Differential amplifier offset voltage minimization independently from common mode voltage adjustment 失效
标题翻译：差分放大器偏移电压最小化独立于共模电压调节
公开(公告)号：US07268624B2
公开(公告)日：2007-09-11
申请号：US11203860
申请日：2005-08-15
申请人： Minhan Chen , Westerfield John Ficken , Louis Lu-Chen Hsu , Steven J. Zier
发明人： Minhan Chen , Westerfield John Ficken , Louis Lu-Chen Hsu , Steven J. Zier
IPC分类号： H03F3/45
CPC分类号： H03F3/45197 , H03F2203/45424 , H03F2203/45431 , H03F2203/45488 , H03F2203/45646
摘要： Offset voltages in differential amplifiers are minimized by controlling compensation currents through the load impedances of the amplifiers. The currents are varied while sensing the polarity of the offset voltage. When the polarity changes, the current values are latched to keep the offset voltage at a minimum.
摘要翻译：通过控制通过放大器的负载阻抗的补偿电流，使差分放大器的失调电压最小化。在检测偏移电压的极性的同时，电流是变化的。当极性变化时，电流值被锁存，以使偏移电压保持最小。

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