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1. 发明授权

US06235632B1 Tungsten plug formation 失效
标题翻译：钨塞形成
公开(公告)号：US06235632B1
公开(公告)日：2001-05-22
申请号：US09006495
申请日：1998-01-13
申请人： Takeshi Nogami , Guarionex Morales , Minh Van Ngo
发明人： Takeshi Nogami , Guarionex Morales , Minh Van Ngo
IPC分类号： H01L2144
CPC分类号： H01L21/76864 , H01L21/76841 , H01L21/76843 , H01L21/76855 , H01L21/76877 , H01L21/76895
摘要： In a preferred embodiment, there is disclosed a method of forming a tungsten plug at the via level. A metal line is formed in a top portion of a first insulating layer. A second insulating layer is formed on the first insulating layer and over an exposed surface of the metal line. An etching process is applied to a region of the second insulating layer formed over the exposed surface of the metal line to create a contact hole within the region. The metal line is exposed at the region. A tungsten nitride thin film is deposited over the second insulating layer and the exposed metal line. A blanket tungsten thin film is deposited to fill the contact hole and to form a planar layer successively to the depositing of the tungsten nitride thin film. The tungsten nitride thin film and the blanket tungsten thin film are chemically mechanically polished until the upper surface of the second insulating layer is exposed.
摘要翻译：在优选实施例中，公开了一种在通孔级形成钨丝塞的方法。金属线形成在第一绝缘层的顶部。在第一绝缘层上和金属线的暴露表面上形成第二绝缘层。对形成在金属线的暴露表面上的第二绝缘层的区域施加蚀刻处理，以在该区域内形成接触孔。金属线暴露在该地区。在第二绝缘层和暴露的金属线上沉积氮化钨薄膜。沉积覆盖的钨薄膜以填充接触孔并且连续地形成平坦层以沉积氮化钨薄膜。化学机械抛光氮化钨薄膜和覆盖钨薄膜，直到第二绝缘层的上表面露出。

2. 发明授权

US06033584A Process for reducing copper oxide during integrated circuit fabrication 失效
标题翻译：在集成电路制造期间减少氧化铜的工艺
公开(公告)号：US06033584A
公开(公告)日：2000-03-07
申请号：US995499
申请日：1997-12-22
申请人： Minh Van Ngo , Guarionex Morales , Takeshi Nogami
发明人： Minh Van Ngo , Guarionex Morales , Takeshi Nogami
IPC分类号： H01L21/311 , H01L21/768 , H01L21/00
CPC分类号： H01L21/31122 , H01L21/76838
摘要： A method of integrated circuit fabrication creating copper interconnect structures wherein the formation of copper oxide is reduced or eliminated by etching away the copper oxide performing an H.sub.2 plasma treatment in a plasma enhanced chemical vapor deposition chamber.
摘要翻译：一种形成铜互连结构的集成电路制造方法，其中通过在等离子体增强化学气相沉积室中蚀刻掉执行H 2等离子体处理的氧化铜来减少或消除氧化铜的形成。

3. 发明授权

US06281584B1 Integrated circuit with improved adhesion between interfaces of conductive and dielectric surfaces 有权
标题翻译：集成电路，具有改善导电和电介质表面界面之间的粘附性
公开(公告)号：US06281584B1
公开(公告)日：2001-08-28
申请号：US09373482
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L2348
CPC分类号： H01L21/31629 , H01L21/76801 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中SiOF电介质层包括其一个边缘处的第一区域，该第一区域耗尽氟到预定深度。

4. 发明授权

US06444593B1 Surface treatment of low-K SiOF to prevent metal interaction 有权
标题翻译：表面处理低K SiOF以防止金属相互作用
公开(公告)号：US06444593B1
公开(公告)日：2002-09-03
申请号：US09373483
申请日：1999-08-12
申请人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
发明人： Minh Van Ngo , Richard J. Huang , Guarionex Morales
IPC分类号： H01L21425
CPC分类号： H01L21/31629 , H01L21/02131 , H01L21/02274 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/76801 , H01L21/76807 , H01L21/76814 , H01L21/76826 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.
摘要翻译：一种在制造半导体产品的方法中使用低电介质SiOF的方法，包括以下步骤：获得SiOF层，并从SiOF层的表面上消耗氟。在优选的实施方案中，耗尽步骤包括用含有氨的等离子体处理SiOF层的表面的步骤。进一步优选的是，经过处理的表面被亚硝酸盐等离子体钝化。本发明还包括半导体芯片，其包括具有至少第一和第二层的集成电路，以及设置在层之间的SiOF的半导体层，其中所述SiOF电介质层包括其一个边缘处的第一区域，所述第一区域耗尽氟至预定深度。

5. 发明授权

US6127193A Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure 失效
公开(公告)号：US6127193A
公开(公告)日：2000-10-03
申请号：US80917
申请日：1998-05-18
申请人： David Bang , Takeshi Nogami , Guarionex Morales , Shekhar Pramanick
发明人： David Bang , Takeshi Nogami , Guarionex Morales , Shekhar Pramanick
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/14 , H01L2924/0002
摘要： A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.

6. 发明授权

US06380556B1 Test structure used to measure metal bottom coverage in trenches and vias/contacts and method for creating the test structure 失效
标题翻译：用于测量沟槽和通孔/触点中的金属底部覆盖度的测试结构以及用于创建测试结构的方法
公开(公告)号：US06380556B1
公开(公告)日：2002-04-30
申请号：US09619292
申请日：2000-07-19
申请人： David Bang , Takeshi Nogami , Guarionex Morales , Shekhar Pramanick
发明人： David Bang , Takeshi Nogami , Guarionex Morales , Shekhar Pramanick
IPC分类号： H01L2940
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A test structure used to measure metal bottom coverage in semiconductor integrated circuits. The metal is deposited in etched trenches, vias and/or contacts created during the integrated circuit manufacturing process. A predetermined pattern of probe contacts are disposed about the semiconductor wafer. Metal deposited in the etched areas is heated to partially react with the underlying and surrounding undoped material. The remaining unreacted metal layer is then removed, and an electrical current is applied to the probe contacts. The resistance of the reacted portion of metal and undoped material is measured to determine metal bottom coverage. Some undoped material may also be removed to measure metal sidewall coverage. The predetermined pattern of probe contacts is preferably arranged in a Kelvin or Vander Paaw structure.
摘要翻译：用于测量半导体集成电路中金属底部覆盖的测试结构。金属沉积在集成电路制造过程中产生的蚀刻沟槽，通孔和/或触点中。探针触点的预定图案围绕半导体晶片设置。沉积在蚀刻区域中的金属被加热以部分地与下面的和周围的未掺杂材料反应。然后去除剩余的未反应的金属层，并且将电流施加到探针接触件。测量金属和未掺杂材料的反应部分的电阻以确定金属底部覆盖。还可以去除一些未掺杂的材料以测量金属侧壁覆盖。探针接触件的预定图案优选地以开尔文或范德瓦结构布置。

7. 发明授权

US6083817A Cobalt silicidation using tungsten nitride capping layer 有权
标题翻译：使用氮化钨覆盖层的硅化硅
公开(公告)号：US6083817A
公开(公告)日：2000-07-04
申请号：US323818
申请日：1999-06-02
申请人： Takeshi Nogami , Robert Chen , Guarionex Morales
发明人： Takeshi Nogami , Robert Chen , Guarionex Morales
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/3205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , Y10S438/902
摘要： A substantially inert capping layer of tungsten nitride is deposited on cobalt layers prior to silicidation, thereby avoiding any substantial interaction with cobalt. The tungsten nitride capping layer also functions as a diffusion barrier preventing oxygen from reaching the silicidation area. The resulting cobalt silicides layer exhibit lower resistivity than those formed employing a titanium capping layer. Embodiments include rapid thermal annealing to initially form a layer of cobalt monosilicide consuming a portion of the cobalt layer, removing the tungsten nitride and unreacted cobalt layer, and rapid thermal annealing again to convert the cobalt monosilicide layer to a low resistivity layer of cobalt disilicide.
摘要翻译：在硅化之前，在钴层上沉积基本惰性的氮化钨覆盖层，从而避免与钴的任何实质的相互作用。氮化钨覆盖层还用作阻止氧气到达硅化区域的扩散阻挡层。所得到的硅化钴层的电阻率比使用钛封盖层的电阻率低。实施方案包括快速热退火以最初形成消耗钴层的一部分的钴单硅酸盐层，去除氮化钨和未反应的钴层，以及再次快速热退火以将一钴硅化物层转化为二硅化钴的低电阻率层。

8. 发明授权

US06281121B1 Damascene metal interconnects using highly directional deposition of barrier and/or seed layers including (III) filling metal 失效
标题翻译：镶嵌金属互连使用屏障和/或种子层的高度定向沉积，包括（III）填充金属
公开(公告)号：US06281121B1
公开(公告)日：2001-08-28
申请号：US09036127
申请日：1998-03-06
申请人： Dirk Dewar Brown , Takeshi Nogami , Guarionex Morales
发明人： Dirk Dewar Brown , Takeshi Nogami , Guarionex Morales
IPC分类号： H01L2144
CPC分类号： H01L21/76843
摘要： An improved damascene metal interconnect for use in a semiconductor integrated circuit. By using highly directional deposition of barrier and/or seed layers the texture of the damascene structure is improved. A first barrier metal layer is deposited in a standard deposition manner, and a second barrier metal is then applied in a highly directional manner. For example, tungsten, titanium and tantalum nitrides can be used as barrier metals. Copper or aluminum based metal is deposited over the second barrier metal, and is then polished by using a chemical mechanical polish. A passivation layer can then be deposited over the interconnect.
摘要翻译：一种用于半导体集成电路的改进的镶嵌金属互连。通过使用势垒和/或种子层的高度定向沉积，改善了镶嵌结构的织构。以标准沉积方式沉积第一阻挡金属层，然后以高度定向的方式施加第二阻挡金属。例如，钨，钛和钽氮化物可以用作阻挡金属。铜或铝基金属沉积在第二阻挡金属上，然后通过使用化学机械抛光抛光。然后可以在互连上沉积钝化层。

9. 发明授权

US6096648A Copper/low dielectric interconnect formation with reduced electromigration 有权
标题翻译：具有减少电迁移的铜/低介电互连形成
公开(公告)号：US6096648A
公开(公告)日：2000-08-01
申请号：US237584
申请日：1999-01-26
申请人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
发明人： Sergey Lopatin , Takeshi Nogami , Robin W. Cheung , Christy Mei-Chu Woo , Guarionex Morales
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76886 , H01L21/76819 , H01L21/76835 , H01L21/76837 , H01L21/76885
摘要： A method of metallizing a semiconductor chip with copper including an inlaid low dielectric constant layer. The method includes the step of depositing a barrier layer on the surface of the semiconductor chip. Next, a copper seed layer is deposited on the barrier layer, and then the copper seed layer is annealed. Microlithography is then performed on the semiconductor chip to form a plurality of wiring line paths with a patterned photoresist layer. After the wiring line paths are formed a copper conductive layer is electroplated to the surface of the semiconductor chip. Next, the patterned photoresist layer is stripped off of the surface of the semiconductor chip. In addition, portions of the barrier layer and the copper seed layer that were covered by the patterned photoresist layer are also removed. A low dielectric constant layer is then deposited on the semiconductor chip to fill the gaps between the newly created copper conductive lines.
摘要翻译：一种用包括嵌入的低介电常数层的铜对半导体芯片进行金属化的方法。该方法包括在半导体芯片的表面上沉积阻挡层的步骤。接下来，在阻挡层上沉积铜籽晶层，然后对铜籽晶层进行退火。然后在半导体芯片上进行微光刻，以形成具有图案化光致抗蚀剂层的多条布线路径。在形成布线路径之后，将铜导电层电镀到半导体芯片的表面。接下来，将图案化的光致抗蚀剂层剥离出半导体芯片的表面。此外，也去除了被图案化光致抗蚀剂层覆盖的阻挡层和铜籽晶层的部分。然后在半导体芯片上沉积低介电常数层以填充新生成的铜导线之间的间隙。

10. 发明授权

US06436850B1 Method of degassing low k dielectric for metal deposition 失效
标题翻译：用于金属沉积的低k电介质的脱气方法
公开(公告)号：US06436850B1
公开(公告)日：2002-08-20
申请号：US09652132
申请日：2000-08-31
申请人： Guarionex Morales
发明人： Guarionex Morales
IPC分类号： H01L214763
CPC分类号： H01L21/76828 , H01L21/3124
摘要： Multi-metallization level semiconductor devices are formed without degrading a low k dielectric gap fill material due to multiple pre-metallization degassing/outgassing heat treatments. Degradation of the low k material is substantially reduced or eliminated by employing time intervals for heat treatment which are not longer than the longest metal deposition step and temperatures below that which the dielectric material decomposes.
摘要翻译：由于多次预金属化除气/除气热处理，多金属化水平半导体器件形成而不降低低k电介质间隙填充材料。通过采用不长于最长金属沉积步骤和低于电介质材料分解温度的温度的热处理时间间隔，可以显着降低或消除低k材料的劣化。

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