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1. 发明授权

US07955964B2 Dishing-free gap-filling with multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US07955964B2
公开(公告)日：2011-06-07
申请号：US12152380
申请日：2008-05-14
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

2. 发明申请

US20110227189A1 Dishing-Free Gap-Filling with Multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US20110227189A1
公开(公告)日：2011-09-22
申请号：US13151666
申请日：2011-06-02
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiun-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L27/04
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

3. 发明授权

US08093120B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08093120B2
公开(公告)日：2012-01-10
申请号：US12839994
申请日：2010-07-20
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

4. 发明授权

US08035165B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08035165B2
公开(公告)日：2011-10-11
申请号：US12341891
申请日：2008-12-22
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.
摘要翻译：提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

5. 发明授权

US08394692B2 Integrating a first contact structure in a gate last process 有权
标题翻译：在最后一个进程中集成第一个接触结构
公开(公告)号：US08394692B2
公开(公告)日：2013-03-12
申请号：US13286276
申请日：2011-11-01
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

6. 发明申请

US20120045889A1 INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后一个过程中集成第一个接触结构
公开(公告)号：US20120045889A1
公开(公告)日：2012-02-23
申请号：US13286276
申请日：2011-11-01
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/28
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.
摘要翻译：提供了一种提供基板的方法，在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。示例性接触特征是双重接触。

7. 发明申请

US20100052075A1 INTEGRATING A FIRST CONTACT STRUCTURE IN A GATE LAST PROCESS 有权
标题翻译：在门窗最后一个过程中集成第一个接触结构
公开(公告)号：US20100052075A1
公开(公告)日：2010-03-04
申请号：US12341891
申请日：2008-12-22
申请人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chiung-Han Yeh , Ming-Yuan Wu , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L29/78 , H01L23/48 , H01L21/04
CPC分类号： H01L29/66606 , H01L21/823814 , H01L21/823871
摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.
摘要翻译：提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。

8. 发明申请

US20100022061A1 Spacer Shape Engineering for Void-Free Gap-Filling Process 有权
标题翻译：无间隙填充过程的间隔形状工程
公开(公告)号：US20100022061A1
公开(公告)日：2010-01-28
申请号：US12179395
申请日：2008-07-24
申请人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Yi-Shien Mor , Chih-Tang Peng , Chiung-Han Yeh , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/336
CPC分类号： H01L21/823481 , H01L21/823468 , H01L21/823475 , H01L29/6653 , H01L29/6656 , H01L29/7833 , H01L29/7843
摘要： A method of forming a semiconductor device includes providing a semiconductor substrate; forming a gate stack on the semiconductor substrate; forming a gate spacer adjacent to a sidewall of the gate stack; thinning the gate spacer; and forming a secondary gate spacer on a sidewall of the gate spacer after the step of thinning the gate spacer.
摘要翻译：一种形成半导体器件的方法包括提供半导体衬底; 在半导体衬底上形成栅叠层; 形成邻近所述栅叠层的侧壁的栅极间隔; 减薄栅间隔; 以及在所述栅极间隔物变薄的步骤之后，在所述栅极间隔物的侧壁上形成次级栅极间隔物。

9. 发明申请

US20090286384A1 Dishing-free gap-filling with multiple CMPs 有权
标题翻译：无间隙填充多个CMP
公开(公告)号：US20090286384A1
公开(公告)日：2009-11-19
申请号：US12152380
申请日：2008-05-14
申请人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
发明人： Ming-Yuan Wu , Kong-Beng Thei , Chiung-Han Yeh , Harry Chuang , Mong-Song Liang
IPC分类号： H01L21/306 , H01L21/283 , H01L21/20 , H01L21/461 , H01L21/302
CPC分类号： H01L21/76883 , H01L21/76229
摘要： A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.
摘要翻译：形成集成电路结构的方法包括提供半导体衬底; 在所述半导体衬底上形成图案化特征，其中在所述图案化特征之间形成间隙; 用第一填充材料填充间隙，其中第一填充材料具有高于图案化特征的顶表面的第一顶表面; 以及执行第一平面化以降低所述第一填充材料的顶表面，直到所述图案化特征的顶表面露出。该方法还包括沉积第二填充材料，其中第二填充材料具有高于图案化特征的顶表面的第二顶表面; 以及执行第二平面化以降低第二填充材料的顶表面，直到图案化特征的顶表面露出。

10. 发明授权

US08735235B2 Integrated circuit metal gate structure and method of fabrication 有权
标题翻译：集成电路金属栅极结构及其制造方法
公开(公告)号：US08735235B2
公开(公告)日：2014-05-27
申请号：US12276015
申请日：2008-11-21
申请人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chiung-Han Yeh , Ming-Yuan Wu , Mong-Song Liang
IPC分类号： H01L21/338
CPC分类号： H01L29/78 , H01L21/28114 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/66545 , H01L29/6659 , H01L29/66606 , H01L29/7833
摘要： A method is provided for forming a metal gate using a gate last process. A trench is formed on a substrate. The profile of the trench is modified to provide a first width at the aperture of the trench and a second width at the bottom of the trench. The profile may be formed by including tapered sidewalls. A metal gate may be formed in the trench having a modified profile. Also provided is a semiconductor device including a gate structure having a larger width at the top of the gate than the bottom of the gate.
摘要翻译：提供一种使用门最后工艺形成金属栅的方法。在基板上形成沟槽。沟槽的轮廓被修改以在沟槽的孔处提供第一宽度，并且在沟槽的底部提供第二宽度。轮廓可以通过包括锥形侧壁形成。金属栅极可以形成在具有改变的轮廓的沟槽中。还提供了一种半导体器件，其包括在栅极顶部具有比栅极的底部更大的宽度的栅极结构。

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