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1. 发明授权

US06462390B1 Multi-film capping layer for a salicide process 有权
标题翻译：用于自杀过程的多层覆盖层
公开(公告)号：US06462390B1
公开(公告)日：2002-10-08
申请号：US09672234
申请日：2000-09-27
申请人： Ming-Shing Chen , Shu-Jen Chen , Jy-Hwang Lin , Kuen-Syh Tseng
发明人： Ming-Shing Chen , Shu-Jen Chen , Jy-Hwang Lin , Kuen-Syh Tseng
IPC分类号： H01L21336
CPC分类号： H01L29/665 , H01L21/28044 , H01L29/4933
摘要： A multi-film capping layer having a cobalt layer, a barrier layer, and a stuffing layer is disclosed, wherein the barrier layer isolates the cobalt layer from the stuffing layer. The multi-film capping layer is formed on a gate transistor and applicable to a self-aligned silicide (salicide) process, so that a sheet resistance of the salicide layer on conductive regions of the gate transistor is significantly reduced. The stuffing layer further prevents entry of oxygen or moisture to the salicide layer, thus no cobalt oxide is formed when RTP is performed. Without formation of the cobalt oxide, the salicide process is free from the bridging issue and the filament issue.
摘要翻译：公开了具有钴层，阻挡层和填充层的多层覆盖层，其中阻挡层将钴层与填料层隔离。多层覆盖层形成在栅极晶体管上并且可应用于自对准硅化物（自对准硅化物）工艺，使得栅极晶体管的导电区域上的自对准硅化物层的薄层电阻显着降低。填充层进一步防止氧化物或水分进入自对准硅化物层，因此在进行RTP时不会形成氧化钴。不形成氧化钴，自对准硅化物工艺没有桥接问题和灯丝问题。

2. 发明授权

US06194298B1 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06194298B1
公开(公告)日：2001-02-27
申请号：US09315797
申请日：1999-05-21
申请人： Ming-Shing Chen , Akira Mao
发明人： Ming-Shing Chen , Akira Mao
IPC分类号： H01L213205
CPC分类号： H01L21/28518 , H01L21/28052 , H01L29/665
摘要： A method of fabricating a semiconductor device is described. A conductive layer is formed on a substrate. A spacer is formed on a sidewall of the conductive layer. A thin metallic layer is formed over the substrate. An ion implantation step is performed. A first seeding layer is formed between the first metallic layer and the conductive layer. A second seeding layer is formed between the first metallic layer and the substrate. A second metallic layer is formed over the substrate. An annealing step is performed to form a self-aligned silicide layer on the conductive layer. The first metallic layer and the second metallic layer that do not react are removed.
摘要翻译：描述制造半导体器件的方法。在基板上形成导电层。在导电层的侧壁上形成间隔物。在衬底上形成薄的金属层。执行离子注入步骤。在第一金属层和导电层之间形成第一种子层。在第一金属层和基板之间形成第二种子层。第二金属层形成在衬底上。执行退火步骤以在导电层上形成自对准的硅化物层。去除不反应的第一金属层和第二金属层。

3. 发明授权

US06319826B1 Method of fabricating barrier layer 失效
标题翻译：制造阻挡层的方法
公开(公告)号：US06319826B1
公开(公告)日：2001-11-20
申请号：US09267875
申请日：1999-03-11
申请人： Ming-Shing Chen , Yung-Chieh Kuo
发明人： Ming-Shing Chen , Yung-Chieh Kuo
IPC分类号： H01L2144
CPC分类号： H01L21/76855 , H01L21/7684 , H01L21/76843 , H01L21/76846
摘要： A method of forming a barrier layer is described. A dielectric layer is formed on a substrate. The dielectric layer comprises an opening exposing a portion of the substrate. A metallic layer, which is conformal to the opening, is formed on the dielectric layer. A first metallic nitride layer, which is conformal to the opening, is formed on the first metallic layer by chemical vapor deposition. The second metallic nitride layer, which is conformal to the opening, is formed on the first metallic nitride layer.
摘要翻译：描述形成阻挡层的方法。在基板上形成电介质层。电介质层包括露出衬底的一部分的开口。在电介质层上形成与开口共形的金属层。通过化学气相沉积在第一金属层上形成与开口共形的第一金属氮化物层。在第一金属氮化物层上形成与开口共形的第二金属氮化物层。

4. 发明申请

US20080025816A1 Multiple-thread screw 审中-公开
标题翻译：多螺纹螺丝
公开(公告)号：US20080025816A1
公开(公告)日：2008-01-31
申请号：US11495969
申请日：2006-07-28
申请人： Ming-Shing Chen , Pau-Ten Lin
发明人： Ming-Shing Chen , Pau-Ten Lin
IPC分类号： F16B25/10
CPC分类号： F16B25/10 , F16B25/0015 , F16B25/0047 , F16B25/0084
摘要： A multiple-thread screw includes: a shank having a tapered end portion and a non-tapered portion, the shank defining an axis and a radial plane radiating from the axis; a first spiral thread formed on the non-tapered portion of the shank and having thread turns, each of which has two diametrically disposed points that cooperatively define a diametrical line inclined at a first thread angle with respect to the radial plane; and two second spiral threads formed on the tapered end portion of the shank and twisted in opposite directions. Each of the second spiral threads has thread turns, each of which has two diametrically disposed points that cooperatively define a diametrical line inclined at a second thread angle with respect to the radial plane. The second thread angle is larger than the first thread angle.
摘要翻译：多螺纹螺钉包括：柄，其具有锥形端部部分和非锥形部分，所述柄部限定轴线和从所述轴线辐射的径向平面; 第一螺旋螺纹形成在柄的非锥形部分上并且具有螺纹，每个螺纹具有两个直径设置的点，其协作地限定相对于径向平面以第一螺纹角倾斜的直径线; 以及形成在柄的锥形端部上并沿相反方向扭转的两个第二螺旋形螺纹。每个第二螺旋螺纹具有螺纹匝，每个螺纹具有两个直径设置的点，其协作地限定相对于径向平面以第二螺纹角倾斜的直径线。第二螺纹角度大于第一螺纹角度。

5. 发明授权

US07592262B2 Method for manufacturing MOS transistors utilizing a hybrid hard mask 有权
标题翻译：利用混合硬掩模制造MOS晶体管的方法
公开(公告)号：US07592262B2
公开(公告)日：2009-09-22
申请号：US11689508
申请日：2007-03-21
申请人： Hui-Ling Huang , Ming-Shing Chen , Nien-Chung Li , Li-Shiun Chen , Hsin Tai
发明人： Hui-Ling Huang , Ming-Shing Chen , Nien-Chung Li , Li-Shiun Chen , Hsin Tai
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/32139 , H01L29/66636
摘要： A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.
摘要翻译：一种制造具有混合硬掩模的MOS晶体管的方法包括：在其上提供具有介电层和多晶硅层的衬底，形成具有中间硬掩模和覆盖多晶硅层上的中间硬掩模的侧壁的间隔物硬掩模的混合硬掩模执行第一蚀刻工艺以通过混合硬掩模蚀刻多晶硅层和电介质层以形成栅极结构，执行第二蚀刻工艺以在栅极结构的两侧在衬底中形成凹槽，并且执行SEG工艺以在每个凹部中形成外延硅层。

6. 发明申请

US20080233746A1 METHOD FOR MANUFACTURING MOS TRANSISTORS UTILIZING A HYBRID HARD MASK 有权
标题翻译：使用混合硬掩模制造MOS晶体管的方法
公开(公告)号：US20080233746A1
公开(公告)日：2008-09-25
申请号：US11689508
申请日：2007-03-21
申请人： Hui-Ling Huang , Ming-Shing Chen , Nien-Chung Li , Li-Shiun Chen , Hsin Tai
发明人： Hui-Ling Huang , Ming-Shing Chen , Nien-Chung Li , Li-Shiun Chen , Hsin Tai
IPC分类号： H01L21/302
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/32139 , H01L29/66636
摘要： A method for manufacturing MOS transistor with hybrid hard mask includes providing a substrate having a dielectric layer and a polysilicon layer thereon, forming a hybrid hard mask having a middle hard mask and a spacer hard mask covering sidewalls of the middle hard mask on the polysilicon layer, performing a first etching process to etch the polysilicon layer and the dielectric layer through the hybrid hard mask to form a gate structure, performing a second etching process to form recesses in the substrate at two sides of the gate structure, and performing a SEG process to form epitaxial silicon layers in each recess.
摘要翻译：一种制造具有混合硬掩模的MOS晶体管的方法包括：在其上提供具有介电层和多晶硅层的衬底，形成具有中间硬掩模和覆盖多晶硅层上的中间硬掩模的侧壁的间隔物硬掩模的混合硬掩模执行第一蚀刻工艺以通过混合硬掩模蚀刻多晶硅层和电介质层以形成栅极结构，执行第二蚀刻工艺以在栅极结构的两侧在衬底中形成凹槽，并且执行SEG工艺以在每个凹部中形成外延硅层。

7. 发明授权

US06291301B1 Fabrication method of a gate junction conductive structure 失效
标题翻译：栅极结导电结构的制造方法
公开(公告)号：US06291301B1
公开(公告)日：2001-09-18
申请号：US09356961
申请日：1999-07-19
申请人： Ming-Shing Chen
发明人： Ming-Shing Chen
IPC分类号： H01L21336
CPC分类号： H01L21/28518 , H01L21/28052 , H01L21/28114 , H01L29/42376 , H01L29/4925 , H01L29/665
摘要： A method of fabricating a gate junction conductive structure is described in which a selective silicon deposition method is used to form a silicon layer of a greater area on the polysilicon gate. A metal silicide process is further conducted on the silicon layer to convert the silicon layer to a metal silicide layer. Since the gate junction surface in forming the metal silicide layer is increased, not only the narrow line effect is prevented, the temperature for the thermal treatment process in forming the metal silicide layer is also lower. As a result, the sheet resistance of the metal silicide layer is lower and the device is more stable.
摘要翻译：描述了制造栅极结导电结构的方法，其中使用选择性硅沉积方法在多晶硅栅极上形成更大面积的硅层。在硅层上进一步进行金属硅化物处理以将硅层转化为金属硅化物层。由于形成金属硅化物层的栅极结表面增加，不仅防止窄线效应，所以形成金属硅化物层时的热处理工艺的温度也较低。结果，金属硅化物层的薄层电阻较低，器件更稳定。

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