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    • 8. 发明申请
    • PHASE CHANGE MEMORY CELL
    • 相变存储器单元
    • US20070278538A1
    • 2007-12-06
    • US11553432
    • 2006-10-26
    • Te-Sheng Chao
    • Te-Sheng Chao
    • H01L29/768
    • G11C11/5678G11C13/0004G11C13/0069G11C2013/0078H01L45/06H01L45/1233H01L45/126H01L45/143H01L45/144H01L45/148Y10S257/903
    • A phase change memory cell is disclosed, including a first electrode and a second electrode, and a plurality of recording layers disposed between the first and second electrodes. The phase of an active region of each of the recording layers can be changed to a crystalline state or an amorphous state by current pulse control and hence respectively has crystalline resistance or amorphous resistance. At least two of the recording layers have different dimensions such that different combinations of the crystalline and amorphous resistance result in at least three different effective resistance values between the first and second electrodes. The phase change memory cell can be realized with the same material of the recording layers and thus can be fabricated with simple and currently developed CMOS fabrication process technologies. Furthermore, the phase change memory is easy to control due to large current programming intervals.
    • 公开了一种相变存储单元,包括第一电极和第二电极,以及设置在第一和第二电极之间的多个记录层。 每个记录层的有源区的相位可以通过电流脉冲控制而变为结晶状态或非晶状态,因此分别具有结晶电阻或无定形电阻。 至少两个记录层具有不同的尺寸,使得晶体和非晶体电阻的不同组合在第一和第二电极之间产生至少三个不同的有效电阻值。 相变存储单元可以用相同的记录层材料实现,因此可以用简单且目前开发的CMOS制造工艺技术来制造。 此外,由于大的电流编程间隔,相变存储器易于控制。
    • 9. 发明授权
    • Phase change memory
    • 相变记忆
    • US08045367B2
    • 2011-10-25
    • US12188293
    • 2008-08-08
    • Te-Sheng Chao
    • Te-Sheng Chao
    • G11C11/00
    • G11C13/004G11C13/0004G11C2013/0054Y10S977/754
    • A phase change memory with a primary memory array, a reference memory array, and a comparison circuit is provided. The electrical characteristic curve of the recording layers of the primary memory units is different from the electrical characteristic curve of the recording layers of the reference memory units. The primary memory array includes at least one primary memory unit to generate at least one sensing signal, wherein each of the primary memory units includes at least one recording layer can be programmed to a first resistance and a second resistance. The reference memory array includes at least one reference memory unit to generate at least one reference signal, wherein each of the reference memory units includes at least one recording layer can be programmed to change its resistance. The comparison circuit compares the sensing signal and the reference signal to generate a comparison result.
    • 提供了具有主存储器阵列,参考存储器阵列和比较电路的相变存储器。 主存储单元的记录层的电特性曲线与参考存储单元的记录层的电特性曲线不同。 主存储器阵列包括至少一个主存储器单元以产生至少一个感测信号,其中每个主存储器单元包括至少一个记录层可被编程为第一电阻和第二电阻。 参考存储器阵列包括至少一个参考存储器单元以产生至少一个参考信号,其中每个参考存储器单元包括至少一个记录层可被编程以改变其电阻。 比较电路比较感测信号和参考信号以产生比较结果。