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1. 发明授权

US08019916B2 Mobile communication terminal system 有权
标题翻译：移动通信终端系统
公开(公告)号：US08019916B2
公开(公告)日：2011-09-13
申请号：US12479012
申请日：2009-06-05
申请人： Ming-Jun Hsiao , Han-Min Cheng , Chih-Chan Yen
发明人： Ming-Jun Hsiao , Han-Min Cheng , Chih-Chan Yen
IPC分类号： G06F3/00
CPC分类号： G06F13/4022
摘要： A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor. The multimedia processor selectively establishes one of a communication connection between the multimedia processor and the serial interface port and a communication connection between the baseband processor and the serial interface port to correspondingly output one of the first serial interface signal and the second serial interface signal to the computer system via the serial interface port.
摘要翻译：移动通信终端系统包括串行接口端口，多媒体输出/输入模块，多媒体处理器，频率信号输出/输入模块和基带处理器。串行接口端口通过串行接口耦合到计算机系统。多媒体输出/输入模块提供第一个输入信号。多媒体处理器处理第一输入信号以产生第一串行接口信号。频率信号输出/输入模块提供第二个输入信号。基带处理器处理第二输入信号以产生到多媒体处理器的第二串行接口信号。多媒体处理器选择性地建立多媒体处理器和串行接口端口之间的通信连接之一以及基带处理器与串行接口端口之间的通信连接，以相应地将第一串行接口信号和第二串行接口信号之一输出到计算机系统通过串行接口端口。

2. 发明申请

US20090307397A1 MOBILE COMMUNICATION TERMINAL SYSTEM 有权
标题翻译：移动通信终端系统
公开(公告)号：US20090307397A1
公开(公告)日：2009-12-10
申请号：US12479012
申请日：2009-06-05
申请人： Ming-Jun Hsiao , Han-Min Cheng , Chih-Chan Yen
发明人： Ming-Jun Hsiao , Han-Min Cheng , Chih-Chan Yen
IPC分类号： G06F13/12
CPC分类号： G06F13/4022
摘要： A mobile communication terminal system includes a serial interface port, a multimedia output/input module, a multimedia processor, a frequency-signal output/input module, and a baseband processor. The serial interface port is coupled to a computer system via a serial interface. The multimedia output/input module provides a first input signal. The multimedia processor processes the first input signal to generate a first serial interface signal. The frequency-signal output/input module provides a second input signal. The baseband processor processes the second input signal to generate a second serial interface signal to the multimedia processor. The multimedia processor selectively establishes one of a communication connection between the multimedia processor and the serial interface port and a communication connection between the baseband processor and the serial interface port to correspondingly output one of the first serial interface signal and the second serial interface signal to the computer system via the serial interface port.
摘要翻译：移动通信终端系统包括串行接口端口，多媒体输出/输入模块，多媒体处理器，频率信号输出/输入模块和基带处理器。串行接口端口通过串行接口耦合到计算机系统。多媒体输出/输入模块提供第一个输入信号。多媒体处理器处理第一输入信号以产生第一串行接口信号。频率信号输出/输入模块提供第二个输入信号。基带处理器处理第二输入信号以产生到多媒体处理器的第二串行接口信号。多媒体处理器选择性地建立多媒体处理器和串行接口端口之间的通信连接之一以及基带处理器与串行接口端口之间的通信连接，以相应地将第一串行接口信号和第二串行接口信号之一输出到计算机系统通过串行接口端口。

3. 发明授权

US5748203A Computer system architecture that incorporates display memory into system memory 失效
标题翻译：将显示存储器并入系统内存的计算机系统架构
公开(公告)号：US5748203A
公开(公告)日：1998-05-05
申请号：US610456
申请日：1996-03-04
申请人： Tsan-Bih Tang , Chih-Chan Yen
发明人： Tsan-Bih Tang , Chih-Chan Yen
IPC分类号： G06F13/16 , G09G5/39
CPC分类号： G09G5/001 , G06F13/1605 , G09G5/39 , G06F3/14 , G09G2360/125
摘要： A computer architecture that incorporates display memory into system memory is disclosed, which comprises a memory, a memory controller and a display controller. Both of the memory controller and the display controller are employed to control access of the memory device having system data and display data stored therein. Built-in signals and an arbiter are provided between the controllers to arbitrate the priorities of the two controllers to access the memory device. Furthermore, request and grant signals are used to initiate the refresh of the main memory to maintain data therein. The control circuits of the two controllers to the memory device are connected to each other to prevent signals contention.
摘要翻译：公开了一种将显示存储器并入系统存储器的计算机架构，其包括存储器，存储器控制器和显示控制器。采用存储器控制器和显示控制器来控制具有存储在其中的系统数据和显示数据的存储器件的访问。在控制器之间提供内置信号和仲裁器，以仲裁两个控制器访问存储设备的优先级。此外，请求和授权信号用于启动主存储器的刷新以在其中维护数据。将两个控制器的控制电路连接到存储器装置以防止信号争用。

4. 发明授权

US07576784B2 Apparatus for acquiring image and method therefor 有权
标题翻译：用于获取图像的方法及其方法
公开(公告)号：US07576784B2
公开(公告)日：2009-08-18
申请号：US11379668
申请日：2006-04-21
申请人： Chih-Chan Yen , Chih-Shih Yu
发明人： Chih-Chan Yen , Chih-Shih Yu
IPC分类号： H04N5/228 , H04N5/222 , H04N5/225 , H04M1/00 , G06K9/22
CPC分类号： H04N9/045 , H04N1/00307 , H04N1/2129 , H04N1/2137 , H04N2201/0065
摘要： An apparatus for acquiring an image and a method therefor. The apparatus is electrically connected to an image sensor for acquiring an acquired image and outputting an original image signal. The apparatus includes an image processor, a data reduction unit and a buffer. The image processor generates a first image signal according to the original image signal. The data reduction unit reduces a data amount of the first image signal to generate a second image signal. The buffer stores the second image signal.
摘要翻译：一种用于获取图像的装置及其方法。该装置电连接到用于获取所获取的图像并输出原始图像信号的图像传感器。该装置包括图像处理器，数据缩小单元和缓冲器。图像处理器根据原始图像信号产生第一图像信号。数据缩小单元减少第一图像信号的数据量以产生第二图像信号。缓冲器存储第二图像信号。

5. 发明申请

US20060238624A1 Apparatus for Acquiring Image and Method Therefor 有权
标题翻译：用于获取图像的方法及其方法
公开(公告)号：US20060238624A1
公开(公告)日：2006-10-26
申请号：US11379668
申请日：2006-04-21
申请人： Chih-Chan Yen , Chih-Shih Yu
发明人： Chih-Chan Yen , Chih-Shih Yu
IPC分类号： H04N5/228
CPC分类号： H04N9/045 , H04N1/00307 , H04N1/2129 , H04N1/2137 , H04N2201/0065
摘要： An apparatus for acquiring an image and a method therefor. The apparatus is electrically connected to an image sensor for acquiring an acquired image and outputting an original image signal. The apparatus includes an image processor, a data reduction unit and a buffer. The image processor generates a first image signal according to the original image signal. The data reduction unit reduces a data amount of the first image signal to generate a second image signal. The buffer stores the second image signal.
摘要翻译：一种用于获取图像的装置及其方法。该装置电连接到用于获取所获取的图像并输出原始图像信号的图像传感器。该装置包括图像处理器，数据缩小单元和缓冲器。图像处理器根据原始图像信号产生第一图像信号。数据缩小单元减少第一图像信号的数据量以产生第二图像信号。缓冲器存储第二图像信号。

6. 发明授权

US5740381A Expandable arbitration architecture for sharing system memory in a computer system 失效
标题翻译：可扩展仲裁架构，用于在计算机系统中共享系统内存
公开(公告)号：US5740381A
公开(公告)日：1998-04-14
申请号：US577555
申请日：1995-12-22
申请人： Chih-Chan Yen
发明人： Chih-Chan Yen
IPC分类号： G06F13/364 , G06F13/00 , G06F13/36
CPC分类号： G06F13/364
摘要： An arbitration bus is arranged between a core logic chip set and a plurality of peripheral devices in order to arbitrate requests by the peripheral devices to use system memory of a computer system. Three or two arbitration signals carried on the arbitration bus. Means are provided to differentiate two levels of priority in each peripheral device. The core logic chip set can make a response pressing or otherwise so as to promote the overall performance. Preemption is provided so that peripheral devices can be overridden without wasting time when it is necessary to do so. Each peripheral device outputs a row address strobe (RAS) signal, all of which are connected together to form a open-collector signal to the core logic chip set for automatically accessing corresponding memory banks of system memory.
摘要翻译：仲裁总线被布置在核心逻辑芯片组和多个外围设备之间，以便仲裁由外围设备使用计算机系统的系统存储器的请求。在仲裁总线上承载三或两个仲裁信号。提供了用于区分每个外围设备中的两个优先级的装置。核心逻辑芯片组可以按照或其他方式做出响应，以提升整体性能。提供抢占，以便外部设备可以在不需要浪费时间的情况下被覆盖。每个外围设备输出行地址选通（RAS）信号，所有这些信号都连接在一起，以形成开放集电极信号到核心逻辑芯片组，用于自动访问系统存储器的相应存储器组。

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