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1. 发明授权

US06744107B1 ESD protection circuit with self-triggered technique 有权
标题翻译：具有自触发技术的ESD保护电路
公开(公告)号：US06744107B1
公开(公告)日：2004-06-01
申请号：US10325892
申请日：2002-12-23
申请人： Ming-Dou Ker , Kuo-Chun Hsu , Wen-Yu Lo
发明人： Ming-Dou Ker , Kuo-Chun Hsu , Wen-Yu Lo
IPC分类号： H01L2972
CPC分类号： H01L27/0266
摘要： An electrostatic discharge protection circuit. The electrostatic discharge protection circuit utilizes the non-uniform triggering of multi-finger gate-grounded NMOS. The source of the finger which has the potential to trigger on is coupled to the base terminal of all the parasitic bipolar transistor of all the other multi-finger gate-ground NMOS structures. Thus, the finger which has the potential to be triggered can be used as a triggering device to trigger the other finger devices during an ESD event. By using this method, the ESD protection NMOS or PMOS, realized with multi-finger layout structure, can be uniformally triggered on to discharge ESD current. Therefore, it can have a high ESD robustness in a small layout area.
摘要翻译：静电放电保护电路。静电放电保护电路利用多指栅极接地NMOS的非均匀触发。具有触发电位的手指的源极耦合到所有其他多指栅极 - 接地NMOS结构的所有寄生双极晶体管的基极端子。因此，具有被触发的可能性的手指可以用作在ESD事件期间触发其他指状装置的触发装置。通过使用这种方法，可以均匀地触发ESD指令，以多指布局结构实现的ESD保护NMOS或PMOS，以放电ESD电流。因此，它可以在小布局区域具有高ESD稳定性。

2. 发明授权

US06885179B1 Low-voltage bandgap reference 失效
标题翻译：低电压带隙基准
公开(公告)号：US06885179B1
公开(公告)日：2005-04-26
申请号：US10708223
申请日：2004-02-17
申请人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
发明人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
IPC分类号： G05F3/16 , G05F3/30
CPC分类号： G05F3/30
摘要： Voltage dividing resistors (R1a, R1b, R2a, R2b) are connected in parallel with diode connected bipolar transistors (Q1, Q2) for splitting the voltage to the inputs of an operational amplifier (62, 82). Current is provided to this arrangement by current sources (I1, I2). When the supply voltage is about 0.85 volts, a temperature insensitive reference voltage of about 200 millivolts is available at the drain of a second transistor (M2, M2).
摘要翻译：分压电阻器（R 1 a，R 1b，R 2 a，R 2 b）与二极管连接的双极晶体管（Q1，Q2）并联连接，用于将电压分配到运算放大器 82）。电流源（I 1，I 2）提供电流。当电源电压约为0.85V时，在第二晶体管（M 2，M 2）的漏极处可获得约200毫伏的温度不敏感参考电压。

3. 发明申请

US20060081927A1 Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation 失效
标题翻译：制造具有相同掩模的ESD保护器件用于LDD和ESD注入的方法
公开(公告)号：US20060081927A1
公开(公告)日：2006-04-20
申请号：US11286406
申请日：2005-11-25
申请人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
发明人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
摘要翻译：一种制造具有ESD保护和内部电路的第一和第二晶体管的半导体器件的方法。该方法包括以下步骤：提供衬底，在衬底上形成第一和第二晶体管的栅极，沉积掩模层，并使用一个单一掩模对掩模层进行构图以去除栅极上的掩模层，漏极区域的一部分的第一晶体管的源极和漏极区域，在没有图案化掩模层的区域下实现ESD注入，去除掩模层并形成栅极的侧壁间隔物，并实现漏极扩散。

4. 发明申请

US20050051848A1 Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation 失效
标题翻译：制造具有相同掩模的ESD保护器件用于LDD和ESD注入的方法
公开(公告)号：US20050051848A1
公开(公告)日：2005-03-10
申请号：US10658772
申请日：2003-09-10
申请人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
发明人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
IPC分类号： H01L21/8238 , H01L23/62 , H01L27/02
CPC分类号： H01L21/823814 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.
摘要翻译：一种制造具有ESD保护和内部电路的第一和第二晶体管的半导体器件的方法。该方法包括以下步骤：提供衬底，在衬底上形成第一和第二晶体管的栅极，沉积掩模层，并使用一个单一掩模对掩模层进行构图以去除栅极上的掩模层，漏极区域的一部分的第一晶体管的源极和漏极区域，在没有图案化掩模层的区域下实现ESD注入，去除掩模层并形成栅极的侧壁间隔物，并实现漏极扩散。

5. 发明授权

US07064942B2 ESD protection circuit with tunable gate-bias 失效
标题翻译： ESD保护电路具有可调栅极偏置
公开(公告)号：US07064942B2
公开(公告)日：2006-06-20
申请号：US10440083
申请日：2003-05-19
申请人： Ming-Dou Ker , Wen-Yu Lo
发明人： Ming-Dou Ker , Wen-Yu Lo
IPC分类号： H02H9/00
CPC分类号： H01L27/0285 , H02H9/046
摘要： An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.
摘要翻译：具有耦合在第一和第二焊盘之间的可调门限偏压的ESD保护电路，用于接收电源电压。 ESD保护电路包括二极管，耦合在二极管的阴极和第一焊盘之间的电阻器，耦合在二极管的阴极和第二焊盘之间的电容器，第一导电类型的第一晶体管，其栅极耦合到二极管的阴极，耦合到二极管的阳极的漏极和耦合到第二焊盘的源极，具有耦合到二极管的阴极的栅极的第二导电类型的第二晶体管，耦合到二极管的阳极的漏极二极管和耦合到第一焊盘的源，以及第一导电类型的第三晶体管，其具有耦合到二极管的阳极的栅极，耦合到第一焊盘的漏极和耦合到第二焊盘的源极。

6. 发明申请

US20060027873A1 Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation 审中-公开
公开(公告)号：US20060027873A1
公开(公告)日：2006-02-09
申请号：US11240475
申请日：2005-10-03
申请人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
发明人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
IPC分类号： H01L23/62
CPC分类号： H01L21/823814 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

7. 发明授权

US06885534B2 Electrostatic discharge protection device for giga-hertz radio frequency integrated circuits with varactor-LC tanks 有权
标题翻译：千兆赫兹射频集成电路与变容二极管LC静电放电保护装置
公开(公告)号：US06885534B2
公开(公告)日：2005-04-26
申请号：US10277640
申请日：2002-10-21
申请人： Ming-Dou Ker , Cheng-Ming Lee , Wen-Yu Lo
发明人： Ming-Dou Ker , Cheng-Ming Lee , Wen-Yu Lo
IPC分类号： H01L27/02 , H02H9/04 , H02H1/00
CPC分类号： H01L27/0251 , H02H9/046
摘要： The present invention relates to a device for protecting high frequency RF integrated circuits from ESD damage. The device comprises at least one varactor-LC circuit tank stacked to avoid the power gain loss by the parasitic capacitance of ESD circuit. The varactor-LC tank could be designed to resonate at the RF operating frequency to avoid the power gain loss from the parasitic capacitance of ESD circuit. Multiple LC-tanks could be stacked for further reduction in the power gain loss. A reverse-biased diode is used as the varactor for both purposes of impedance matching and effective ESD current discharging. Because the inductor is made of metal, both the inductor and the varactor can discharge ESD current when ESD condition happens. It has a high enough ESD level to prevent ESD discharge.
摘要翻译：本发明涉及用于保护高频RF集成电路免受ESD损坏的装置。该装置包括至少一个堆叠的变容二极管LC电路箱，以避免由ESD电路的寄生电容引起的功率增益损失。变容二极管LC罐可以设计为以RF工作频率谐振，以避免ESD电路的寄生电容产生的功率增益损耗。可以堆叠多个液相色谱柱，以进一步降低功率增益损失。反向偏置二极管用作变容二极管，用于阻抗匹配和有效的ESD电流放电。由于电感由金属制成，所以当ESD条件发生时，电感和变容二极管均可放电ESD电流。它具有足够高的ESD电平以防止ESD放电。

8. 发明授权

US07049659B2 Method of manufacturing an ESD protection device with the same mask for both LDD and ESD implantation 失效
公开(公告)号：US07049659B2
公开(公告)日：2006-05-23
申请号：US10658772
申请日：2003-09-10
申请人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
发明人： Ming-Dou Ker , Hsin-Chyh Hsu , Wen-Yu Lo
IPC分类号： H01L29/94
CPC分类号： H01L21/823814 , H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device having a first and second transistor of an ESD protection and internal circuit respectively. The method includes the steps of providing a substrate, forming gates of the first and second transistor on the substrate, depositing a mask layer and patterning the mask layer using one single mask to remove the mask layer on the gates, a portion of a drain region of the first transistor, and a source and drain region of the second transistor, implementing ESD implantation under the regions without the patterned mask layer, removing the mask layer and forming sidewall spacers of the gates, and implementing drain diffusion.

9. 发明授权

US06987416B2 Low-voltage curvature-compensated bandgap reference 失效
标题翻译：低压曲率补偿带隙基准
公开(公告)号：US06987416B2
公开(公告)日：2006-01-17
申请号：US10708222
申请日：2004-02-17
申请人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
发明人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.
摘要翻译：减法器连接在p沟道带隙基准单元和n沟道带隙基准单元之间。减法器包括连接到p沟道带隙基准单元的两个NPN晶体管和连接到n沟道带隙基准单元的两个PNP晶体管。减法器取得由p沟道和n沟道带隙参考单元产生的两个电流的差异，并在输出电阻器上产生小于1伏特的温度不敏感和曲率补偿参考电压。

10. 发明申请

US20050264345A1 LOW-VOLTAGE CURVATURE-COMPENSATED BANDGAP REFERENCE 失效
标题翻译：低电压曲线补偿参考
公开(公告)号：US20050264345A1
公开(公告)日：2005-12-01
申请号：US10708222
申请日：2004-02-17
申请人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
发明人： Ming-Dou Ker , Ching-Yun Chu , Wen-Yu Lo
IPC分类号： G05F1/10 , G05F3/30
CPC分类号： G05F3/30
摘要： A subtractor is connected between a p-channel bandgap reference unit and an n-channel bandgap reference unit. The subtractor includes two NPN transistors connected to the p-channel bandgap reference unit, and two PNP transistors connected to the n-channel bandgap reference unit. The subtractor takes the difference of the two currents produced by the p-channel and n-channel bandgap reference units and generates a temperature insensitive and curvature-compensated reference voltage of less than one volt across an output resistor.
摘要翻译：减法器连接在p沟道带隙基准单元和n沟道带隙基准单元之间。减法器包括连接到p沟道带隙基准单元的两个NPN晶体管和连接到n沟道带隙基准单元的两个PNP晶体管。减法器取得由p沟道和n沟道带隙参考单元产生的两个电流的差异，并在输出电阻器上产生小于1伏特的温度不敏感和曲率补偿参考电压。

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