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    • 5. 发明授权
    • Detergent composition
    • 洗涤剂组成
    • US07923426B2
    • 2011-04-12
    • US12475712
    • 2009-06-01
    • Kenneth Nathan PriceHiroshi OhQing ChenMing TangSuxuan GongLucia Mendez-Mata
    • Kenneth Nathan PriceHiroshi OhQing ChenMing TangSuxuan GongLucia Mendez-Mata
    • C11D17/00
    • C11D1/143C11D1/146C11D1/22
    • A detergent composition comprising: a non-sulphated anionic surfactant, alkyl sulphate surfactant(s) of formula R2—O—SO3−M+, with R2 being a linear or branched, substituted or unsubstituted, optionally alkoxylated, C6-C18 alkyl and with M+ being a proton or a cation which provides charge neutrality, and wherein the alkyl sulphate surfactant(s) of formula R2—O—SO3−M+, comprises from 85% to 100% by weight of alkyl sulphate surfactant(s) of formula R1—O—SO3−M+, with R1 being a linear or branched, substituted or unsubstituted, optionally alkoxylated, C6-C14 alkyl and with M+ being a proton or a cation which provides charge neutrality, wherein the composition comprises from 0 to 20% of zeolite, and wherein the composition does not comprise from 40% to 43% by weight of sodium chloride.
    • 一种洗涤剂组合物,其包含:非硫酸化的阴离子表面活性剂,式R 2 -O-SO 3 -M +的烷基硫酸盐表面活性剂,其中R 2是直链或支链的取代或未取代的,任选烷氧基化的C 6 -C 18烷基和M + 是提供电荷中性的质子或阳离子,并且其中式R2-O-SO3-M +的烷基硫酸盐表面活性剂包含85重量%至100重量%的式R1- O-SO 3 -M +,其中R 1是直链或支链的取代或未取代的任选烷氧基化的C 6 -C 14烷基,并且M +是提供电荷中性的质子或阳离子,其中所述组合物包含0至20%的沸石 ,并且其中所述组合物不包含40重量%至43重量%的氯化钠。
    • 9. 发明申请
    • Flash memory structure and fabrication method thereof
    • 闪存结构及其制造方法
    • US20060033147A1
    • 2006-02-16
    • US10981653
    • 2004-11-05
    • Ming Tang
    • Ming Tang
    • H01L21/336H01L29/76
    • H01L29/66825H01L27/115H01L27/11553H01L29/40114H01L29/7885
    • A flash memory structure comprises a semiconductor substrate, a source region, a drain region, a first insulating dielectric layer, a floating gate, a second insulating dielectric layer, and a control gate. The semiconductor substrate has a first top surface and a second top surface that is lower than the first top surface. The source region and the drain region are respectively in the second top surface and the first top surface of the semiconductor substrate, and the semiconductor substrate connecting the source region and the drain region is a vertical channel region. The whole channel region is covered by the first insulating dielectric layer, the floating gate, the second insulating dielectric layer, and the control gate in turn.
    • 闪存结构包括半导体衬底,源极区,漏极区,第一绝缘介电层,浮栅,第二绝缘介质层和控制栅。 半导体衬底具有比第一顶表面低的第一顶表面和第二顶表面。 源极区域和漏极区域分别位于半导体衬底的第二顶表面和第一顶表面中,并且连接源极区域和漏极区域的半导体衬底是垂直沟道区域。 整个通道区域依次由第一绝缘介电层,浮置栅极,第二绝缘介电层和控制栅极覆盖。