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1. 发明申请

US20110127556A1 ORGANIC LIGHT EMITTING DIODE LIGHTING APPARATUS 有权
标题翻译：有机发光二极管照明设备
公开(公告)号：US20110127556A1
公开(公告)日：2011-06-02
申请号：US12885374
申请日：2010-09-17
申请人： Min-Woo LEE , Ok-Keun SONG , Young-Mo KOO , Jae-Goo LEE , Sung-Jin CHOI
发明人： Min-Woo LEE , Ok-Keun SONG , Young-Mo KOO , Jae-Goo LEE , Sung-Jin CHOI
IPC分类号： H01L33/26
CPC分类号： H01L51/5246
摘要： An organic light emitting diode lighting apparatus includes: a substrate main body including a sealing area and a sealing line surrounding the sealing area; a plurality of first line electrodes of which both ends are located within the sealing area; a plurality of second line electrodes, at least one end of which is located outside the sealing area; an encapsulating member disposed to face the substrate main body; a sealant disposed on the sealing line to bond the substrate main body and the encapsulating member and seal the sealing area; a first connection member coupled to the ends of the plurality of first line electrodes within the sealing area; and a second connection member coupled to the ends of the plurality of second line electrodes outside the sealing area.
摘要翻译：一种有机发光二极管照明装置，包括：基板主体，包括密封区域和围绕所述密封区域的密封线; 多个第一线电极，其两端位于密封区域内; 多个第二线电极，其至少一端位于所述密封区域的外部; 设置成面对所述基板主体的封装构件; 密封剂，其设置在所述密封线上，以结合所述基板主体和所述封装构件并密封所述密封区域; 耦合到密封区域内的多个第一线电极的端部的第一连接构件; 以及耦合到密封区域外部的多个第二线电极的端部的第二连接构件。

2. 发明申请

US20110068688A1 ORGANIC LIGHT EMITTING LIGHTING APPARATUS 有权
标题翻译：有机发光照明设备
公开(公告)号：US20110068688A1
公开(公告)日：2011-03-24
申请号：US12878290
申请日：2010-09-09
申请人： Sung-Jin CHOI , Ok-Keun SONG , Young-Mo KOO , Doo-Hwan KIM , Min-Woo LEE , Jae-Goo LEE
发明人： Sung-Jin CHOI , Ok-Keun SONG , Young-Mo KOO , Doo-Hwan KIM , Min-Woo LEE , Jae-Goo LEE
IPC分类号： H01L33/00 , F21V23/00
CPC分类号： H01L51/5203 , H01L2251/5361 , H01L2251/568
摘要： An organic light emitting lighting device that includes a transparent substrate, a first electrode layer formed on the substrate, an organic emission layer formed on the first electrode layer, a second electrode line formed of a plurality of second electrode lines disposed in parallel with each other on the organic emission layer, a first fuse unit having one end connected with the first electrode layer, and a plurality of second fuses having one end respectively connected to one end of the plurality of second electrode lines.
摘要翻译：一种有机发光照明装置，包括透明基板，形成在基板上的第一电极层，形成在第一电极层上的有机发光层，由彼此平行布置的多个第二电极线形成的第二电极线在所述有机发光层上形成有与所述第一电极层连接的一端的第一熔丝单元，以及分别与所述多个第二电极线的一端连接的一端的多个第二熔丝。

3. 发明申请

US20140021632A1 VERTICAL TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：垂直型半导体器件及其制造方法
公开(公告)号：US20140021632A1
公开(公告)日：2014-01-23
申请号：US13865580
申请日：2013-04-18
申请人： Jae-Goo LEE , Jin-Soo LIM
发明人： Jae-Goo LEE , Jin-Soo LIM
IPC分类号： G11C5/06 , H01L21/48
CPC分类号： G11C5/063 , G11C8/14 , H01L21/486 , H01L21/76816 , H01L23/485 , H01L23/5226 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L2924/0002 , H01L2924/00
摘要： A vertical type semiconductor device includes a pillar structure protruding from a top surface of a substrate of a cell array region. Word lines extend while surrounding the pillar structure. Word line contacts contact edges of the word lines functioning as pad portions. An insulating interlayer pattern is provided on the substrate of a peripheral circuit region, which is disposed at an outer peripheral portion of the cell array region. A first contact plug contacts the substrate of the peripheral circuit region. A second contact plug contacts a top surface of the first contact plug and has a top surface aligned on the same plane with the top surfaces of the word line contacts. The first and second contact plugs are stacked in the peripheral circuit region, so the failure of the vertical type semiconductor device is reduced.
摘要翻译：垂直型半导体器件包括从电池阵列区域的衬底的顶表面突出的柱结构。字线在围绕柱结构的同时延伸。字线接触用作焊盘部分的字线的接触边缘。绝缘层间图案设置在外围电路区域的基板上，该外围电路区域设置在电池阵列区域的外周部。第一接触插塞接触外围电路区域的衬底。第二接触插塞接触第一接触插塞的顶表面，并且具有与字线触点的顶表面在同一平面上对准的顶表面。第一和第二接触插塞堆叠在外围电路区域中，因此垂直型半导体器件的故障降低。

4. 发明申请

US20110032279A1 DISPLAY DRIVER CIRCUIT AND DISPLAY DEVICE 失效
标题翻译：显示驱动电路和显示设备
公开(公告)号：US20110032279A1
公开(公告)日：2011-02-10
申请号：US12766508
申请日：2010-04-23
申请人： In-Suk KIM , Jae-Goo LEE
发明人： In-Suk KIM , Jae-Goo LEE
IPC分类号： G09G5/10
CPC分类号： G09G3/2007 , G09G3/3696 , G09G2320/0252 , G09G2320/0276 , G09G2330/021
摘要： A display driver circuit and a display device are provided. The display driver circuit may have positive and negative resistor strings that are symmetrically formed and include a plurality of resistors, and applies a gamma voltage to one of the positive and negative resistor strings in response to a polarity selection signal, thereby generating and outputting a positive grayscale voltage and a negative grayscale voltage.
摘要翻译：提供显示驱动电路和显示装置。显示驱动器电路可以具有对称地形成并且包括多个电阻器的正和负电阻器串，并且响应于极性选择信号，向正电阻器串和负电阻器串中的一个施加伽马电压，从而产生并输出正灰度电压和负灰度电压。

5. 发明申请

US20070111437A1 SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：包括存储节点的半导体器件及其制造方法
公开(公告)号：US20070111437A1
公开(公告)日：2007-05-17
申请号：US11621507
申请日：2007-01-09
申请人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
发明人： Chang-Hyun CHO , Tae-Young CHUNG , Cheol-Ju YUN , Jae-Goo LEE , Ju-Yong LEE
IPC分类号： H01L21/8242
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L28/91
摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.
摘要翻译：一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

6. 发明申请

US20080043044A1 METHOD AND CIRCUIT OF SELECTIVELY GENERATING GRAY-SCALE VOLTAGE 有权
标题翻译：选择性生成灰度电压的方法和电路
公开(公告)号：US20080043044A1
公开(公告)日：2008-02-21
申请号：US11755834
申请日：2007-05-31
申请人： Jae-Hyuck WOO , Jae-Goo LEE
发明人： Jae-Hyuck WOO , Jae-Goo LEE
IPC分类号： G09G5/10
CPC分类号： G09G3/3696 , G09G3/3607 , G09G3/3688 , G09G2310/027 , G09G2310/0297 , G09G2320/0209 , G09G2320/0233 , G09G2320/0247 , G09G2320/0673
摘要： Embodiments of the present invention provide a method for driving a liquid crystal display (LCD) device using gray-scale voltages whose dynamic ranges are different from each other depending on pixel color. The gray-scale voltages are output to a source line driver. Embodiments of the invention also provide a gray-scale voltage generation circuit coupled to a LCD source line driver. The disclosed method and circuit reduce coupling phenomena in source lines to substantially remove artifacts such as stripes or flicker in an LCD device.
摘要翻译：本发明的实施例提供一种使用其动态范围根据像素颜色彼此不同的灰度电压来驱动液晶显示（LCD）装置的方法。灰度电压被输出到源极线驱动器。本发明的实施例还提供了耦合到LCD源极线驱动器的灰度电压产生电路。所公开的方法和电路减少了源极线中的耦合现象，以便基本上去除LCD器件中的伪影，例如条纹或闪烁。

7. 发明申请

US20170229476A1 NON-VOLATILE MEMORY DEVICE 审中-公开
公开(公告)号：US20170229476A1
公开(公告)日：2017-08-10
申请号：US15485334
申请日：2017-04-12
申请人： Jong-Won KIM , Chang-Seok KANG , Young-Woo PARK , Jae-Goo LEE , Jae-Duk LEE
发明人： Jong-Won KIM , Chang-Seok KANG , Young-Woo PARK , Jae-Goo LEE , Jae-Duk LEE
IPC分类号： H01L27/11582 , H01L27/11565 , H01L23/528 , H01L27/1157
CPC分类号： H01L27/11582 , H01L23/5283 , H01L27/11565 , H01L27/1157
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

8. 发明申请

US20170092651A1 NON-VOLATILE MEMORY DEVICE 有权
公开(公告)号：US20170092651A1
公开(公告)日：2017-03-30
申请号：US15264902
申请日：2016-09-14
申请人： Jong-Won KIM , Chang-Seok KANG , Young-Woo PARK , Jae-Goo LEE , Jae-Duk LEE
发明人： Jong-Won KIM , Chang-Seok KANG , Young-Woo PARK , Jae-Goo LEE , Jae-Duk LEE
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11582
摘要： A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

9. 发明申请

US20080088029A1 SEMICONDUCTOR DEVICE HAVING CONTACT BARRIER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有接触障碍物的半导体器件及其制造方法
公开(公告)号：US20080088029A1
公开(公告)日：2008-04-17
申请号：US11933039
申请日：2007-10-31
申请人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
发明人： Hyeong-Sun HONG , Jae-Goo LEE , Dong-Hyun KIM , Sung-Un KWON , Sang-Joon PARK , Nam-Jung KANG
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L27/0207 , H01L21/76802 , H01L27/10808 , H01L27/10855 , H01L27/10885 , Y10S257/905
摘要： A semiconductor device having a contact barrier for insulating contacts with a large aspect ratio and having a fine pitch between adjacent conductive lines and a method of manufacturing the same are provided. The semiconductor device includes a buried contact formed in a region between two adjacent first conductive lines and two adjacent second conductive lines. Insulating lines define a width of the buried contact. To form the contact barrier, an interlayer dielectric layer formed on the second conductive lines is patterned to form a space and an insulating line having an etching ratio different from the interlayer dielectric layer is formed in the space. The interlayer dielectric layer is selectively wet etched relative to an insulating layer covering the second conductive line and the first insulating line to form buried contact hole. The buried contact hole is filled with conductive material to form a buried contact.
摘要翻译：提供一种半导体器件，其具有用于具有大纵横比的绝缘触点的接触屏障，并且在相邻的导线之间具有微细的间距及其制造方法。半导体器件包括形成在两个相邻的第一导电线和两个相邻的第二导电线之间的区域中的掩埋接触。绝缘线限定埋入触点的宽度。为了形成接触屏障，形成在第二导线上的层间电介质层形成空间，并且在该空间中形成具有与层间电介质层不同的蚀刻比的绝缘线。相对于覆盖第二导线和第一绝缘线的绝缘层选择性地湿蚀刻层间电介质层以形成掩埋接触孔。埋入的接触孔填充有导电材料以形成掩埋接触。

10. 发明申请

US20070218682A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070218682A1
公开(公告)日：2007-09-20
申请号：US11751515
申请日：2007-05-21
申请人： Jae-Goo LEE , Cheol-Ju YUN
发明人： Jae-Goo LEE , Cheol-Ju YUN
IPC分类号： H01L21/4763
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10885
摘要： Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.
摘要翻译：具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。在蚀刻部分的侧壁上形成第一间隔物。蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。同时，第二绝缘层的第二间隔件形成在第一间隔件下面。第二导电层填充存储节点接触孔以形成存储节点接触焊盘。由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

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