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    • 1. 发明授权
    • Clock timing adjustment device and continuous time delta-sigma modulator using the same
    • 时钟定时调整装置和使用其的连续时间Δ-Σ调制器
    • US08482443B2
    • 2013-07-09
    • US13184182
    • 2011-07-15
    • Yi-Gyeong KimBong Chan KimMin-Hyung ChoJong-Kee Kwon
    • Yi-Gyeong KimBong Chan KimMin-Hyung ChoJong-Kee Kwon
    • H03M3/00
    • H03M3/372H03M3/458
    • Provided is a clock timing adjustment device for adjusting a time difference of clocks and a delta-sigma modulator. The clock timing adjustment device includes a power detection unit and a timing adjustment unit. The power detection unit receives input signals which are generated using pairs of first and second clocks having a plurality of clock time differences and respectively correspond to the clock time differences, detects powers of the input signals, and outputs a control signal corresponding to a clock time difference where the power is minimized. The timing adjustment unit receives a reference clock and the control signal and outputs the first and second clocks having the clock time difference where the power is minimized from the reference clock according to the control signal.
    • 提供了一种用于调整时钟的时间差和Δ-Σ调制器的时钟定时调整装置。 时钟定时调整装置包括功率检测单元和定时调整单元。 功率检测单元接收使用具有多个时钟时间差的第一和第二时钟对生成的输入信号,并分别对应于时钟时间差,检测输入信号的功率,并输出对应于时钟时间的控制信号 功率最小化的差异。 定时调整单元接收参考时钟和控制信号,并根据控制信号从参考时钟输出具有最小功率的时钟时间差的第一和第二时钟。
    • 3. 发明授权
    • Current switch driving circuit and digital to analog converter
    • 电流开关驱动电路和数模转换器
    • US08542139B2
    • 2013-09-24
    • US13310606
    • 2011-12-02
    • Min-Hyung ChoYi-Gyeong KimJong-Kee Kwon
    • Min-Hyung ChoYi-Gyeong KimJong-Kee Kwon
    • H03M1/00
    • H03K17/04106H03M1/06H03M1/66
    • Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.
    • 提供了产生用于驱动电流开关的信号的电流开关驱动电路和使用该电流开关的数模转换器。 电流开关驱动电路包括:第一PMOS晶体管,源极端子连接到电源端子,栅极端子接收输入信号,漏极端子输出驱动信号;漏极端子连接的NMOS晶体管 到第一PMOS晶体管的漏极端子,并且栅极端子接收输入信号;第二PMOS晶体管,其源极端子连接到NMOS晶体管的源极端子,栅极端子连接到偏置电压端子, 并且漏极端子连接到接地端子,并且使得允许第二PMOS晶体管恒定地处于导通状态的控制电流源。
    • 4. 发明申请
    • CURRENT SWITCH DRIVING CIRCUIT AND DIGITAL TO ANALOG CONVERTER
    • 电流开关驱动电路和数字到模拟转换器
    • US20120154189A1
    • 2012-06-21
    • US13310606
    • 2011-12-02
    • Min-Hyung CHOYi-Gyeong KimJong-Kee Kwon
    • Min-Hyung CHOYi-Gyeong KimJong-Kee Kwon
    • H03M1/66H03B1/00
    • H03K17/04106H03M1/06H03M1/66
    • Provided are a current switch driving circuit generating a signal for driving a current switch, and a digital-to-analog converter using the same. The current switch driving circuit includes a first PMOS transistor in which a source terminal is connected to a power supply terminal, a gate terminal receives an input signal, and a drain terminal outputs a driving signal, an NMOS transistor in which a drain terminal is connected to the drain terminal of the first PMOS transistor, and a gate terminal receives the input signal, a second PMOS transistor in which a source terminal is connected to a source terminal of the NMOS transistor, a gate terminal is connected to a bias voltage terminal, and a drain terminal is connected to a ground terminal, and a control current source allowing the second PMOS transistor to be maintained constantly in an ON state.
    • 提供了产生用于驱动电流开关的信号的电流开关驱动电路和使用该电流开关的数模转换器。 电流开关驱动电路包括:第一PMOS晶体管,源极端子连接到电源端子,栅极端子接收输入信号,漏极端子输出驱动信号;漏极端子连接的NMOS晶体管 到第一PMOS晶体管的漏极端子,并且栅极端子接收输入信号;第二PMOS晶体管,其源极端子连接到NMOS晶体管的源极端子,栅极端子连接到偏置电压端子, 并且漏极端子连接到接地端子,并且使得允许第二PMOS晶体管恒定地处于导通状态的控制电流源。