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    • 10. 发明申请
    • METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY
    • 具有对准键的半导体器件的制造方法及其制造的半导体器件
    • US20090087962A1
    • 2009-04-02
    • US12325694
    • 2008-12-01
    • Min-Hee ChoYoo-Sang HwangByung-Hyun Lee
    • Min-Hee ChoYoo-Sang HwangByung-Hyun Lee
    • H01L21/02
    • H01L27/10894H01L23/544H01L27/10814H01L28/91H01L2223/54426H01L2223/54453H01L2223/5446H01L2924/0002H01L2924/00
    • In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.
    • 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案,从而在划线路区域中形成对准键图案,同时在单元区域中形成存储节点接触开口。