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1. 发明申请

US20090218679A1 CHIP PACKAGE AND PROCESS THEREOF 审中-公开
标题翻译：芯片包装及其处理
公开(公告)号：US20090218679A1
公开(公告)日：2009-09-03
申请号：US12437817
申请日：2009-05-08
申请人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
发明人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
IPC分类号： H01L23/538
CPC分类号： H01L23/04 , H01L21/481 , H01L21/4846 , H01L23/3114 , H01L23/481 , H01L23/49805 , H01L23/552 , H01L24/02 , H01L27/14618 , H01L2224/0401 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface.
摘要翻译：公开了一种芯片封装。芯片封装包括芯片，多个接合焊盘，多个连接线和刚性盖。芯片具有沿着芯片的至少边缘布置的多个凹槽，并且还具有有源表面和背面。接合焊盘设置在有源表面上，并且接合焊盘分别布置成对应于凹部。连接线分别设置在芯片的边缘处的凹部的表面上。对于每个连接线，连接线的第一端连接到一个接合焊盘，并且连接线的第二端延伸到背面以作为端子焊盘。刚性盖位于活动表面上，而不覆盖活动表面上的接合垫。

2. 发明申请

US20050212132A1 Chip package and process thereof 审中-公开
标题翻译：芯片封装及其工艺
公开(公告)号：US20050212132A1
公开(公告)日：2005-09-29
申请号：US10810436
申请日：2004-03-25
申请人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
发明人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
IPC分类号： H01L23/04 , H01L23/31 , H01L23/48 , H01L23/485 , H01L23/498 , H01L23/552
CPC分类号： H01L23/04 , H01L21/481 , H01L21/4846 , H01L23/3114 , H01L23/481 , H01L23/49805 , H01L23/552 , H01L24/02 , H01L27/14618 , H01L2224/0401 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： The chip package and the process thereof are disclosed. In the chip package, a rigid cover is disposed on the active surface of the chip to protect the active surface of the chip and enhance the structural strength of the chip package. Further, if the material of the rigid cover is a thermal conductive material such as Cu or Al alloy, the heat-spread ability of the chip package can be enhanced. If the rigid cover is made of an electrical conductive material and electrically connected to the ground, the electromagnetic interference (EMI) to the chip package can be reduced. It should be noted that the chip packaging process can form a plurality of the terminal pads on the backside of the chip so that the chip package can be connected to the PCB or substrate via these terminal pads.
摘要翻译：公开了芯片封装及其工艺。在芯片封装中，刚性盖布置在芯片的有源表面上以保护芯片的有源表面并增强芯片封装的结构强度。此外，如果刚性盖的材料是诸如Cu或Al合金的导热材料，则可以提高芯片封装的散热能力。如果刚性盖由导电材料制成并且电连接到地面，则可以减小对芯片封装的电磁干扰（EMI）。应当注意，芯片封装处理可以在芯片的背面上形成多个端子焊盘，使得芯片封装可以经由这些端子焊盘连接到PCB或衬底。

3. 发明授权

US07534653B2 Chip packaging process 有权
标题翻译：芯片封装工艺
公开(公告)号：US07534653B2
公开(公告)日：2009-05-19
申请号：US11563514
申请日：2006-11-27
申请人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
发明人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
IPC分类号： H01L21/00
CPC分类号： H01L23/04 , H01L21/481 , H01L21/4846 , H01L23/3114 , H01L23/481 , H01L23/49805 , H01L23/552 , H01L24/02 , H01L27/14618 , H01L2224/0401 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： A chip packaging process includes providing a wafer, having an active surface and a backside. The wafer has a first chip area and a second chip area adjacent to the first chip area. The wafer has several first and second bond pads on the active surface in the first and second chip areas respectively. Several through holes are formed on the wafer. The through holes pass through the wafer and connect the active surface and the backside. The through. holes are arranged between the first chip area and the second chip area. Several connecting lines are formed on peripheral surfaces of the through holes. Each of the connecting lines has a first end portion extending on the active surface and a second portion extending on the backside. Each the first end portion is electrically connected to one of the first bond pads and one of the second bond pads.
摘要翻译：芯片封装工艺包括提供具有活性表面和背面的晶片。晶片具有与第一芯片区域相邻的第一芯片区域和第二芯片区域。晶片在第一和第二芯片区域的有源表面上分别具有多个第一和第二接合焊盘。在晶片上形成几个通孔。通孔穿过晶片并连接有源表面和背面。通过。在第一芯片区域和第二芯片区域之间布置有孔。在通孔的周面形成有多条连接线。每个连接线具有在活动表面上延伸的第一端部部分和在背侧上延伸的第二部分。每个第一端部电连接到第一接合焊盘之一和第二接合焊盘之一。

4. 发明申请

US20080185710A1 CHIP PACKAGE AND PROCESS THEREOF 审中-公开
标题翻译：芯片包装及其处理
公开(公告)号：US20080185710A1
公开(公告)日：2008-08-07
申请号：US12100631
申请日：2008-04-10
申请人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
发明人： Min-Chih Hsuan , Kai-Kuang Ho , Kuo-Ming Chen , Kuang-Hui Tang
IPC分类号： H01L23/498
CPC分类号： H01L23/04 , H01L21/481 , H01L21/4846 , H01L23/3114 , H01L23/481 , H01L23/49805 , H01L23/552 , H01L24/02 , H01L27/14618 , H01L2224/0401 , H01L2224/16 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/16235 , H01L2924/00
摘要： The chip package and the process thereof are disclosed. The chip package comprises a chip and a rigid cover. The chip has a plurality of bond pads formed thereon. The rigid cover is located on the chip and has a plurality of openings formed therein, wherein the openings expose the bond pads on the chip respectively.
摘要翻译：公开了芯片封装及其工艺。芯片封装包括芯片和刚性盖。芯片具有形成在其上的多个接合焊盘。刚性盖位于芯片上并且具有形成在其中的多个开口，其中开口分别暴露芯片上的接合焊盘。

5. 发明申请

US20060065976A1 METHOD FOR MANUFACTURING WAFER LEVEL CHIP SCALE PACKAGE STRUCTURE 有权
标题翻译：制造水平流片尺寸包装结构的方法
公开(公告)号：US20060065976A1
公开(公告)日：2006-03-30
申请号：US10711536
申请日：2004-09-24
申请人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
发明人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
IPC分类号： H01L23/48
CPC分类号： H01L24/97 , H01L23/15 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13111 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/29075 , H01L2224/83851 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
摘要翻译：本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。晶片通过其上的凸块或焊盘与玻璃基板连接。在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。之后，进行分割步骤，并获得多个芯片级封装结构。

6. 发明授权

US07170167B2 Method for manufacturing wafer level chip scale package structure 有权
标题翻译：制造晶圆级芯片级封装结构的方法
公开(公告)号：US07170167B2
公开(公告)日：2007-01-30
申请号：US10711536
申请日：2004-09-24
申请人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
发明人： Min-Chih Hsuan , Paul Chen , Hermen Liu , Kun-Chih Wang , Kai-Kuang Ho
IPC分类号： H01L23/48
CPC分类号： H01L24/97 , H01L23/15 , H01L23/3114 , H01L23/3128 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L24/81 , H01L24/83 , H01L2224/05001 , H01L2224/05026 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/05666 , H01L2224/13111 , H01L2224/16225 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/8121 , H01L2224/81815 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/29075 , H01L2224/83851 , H01L2224/05099 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.
摘要翻译：本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。晶片通过其上的凸块或焊盘与玻璃基板连接。在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。之后，进行分割步骤，并获得多个芯片级封装结构。

7. 发明授权

US07192847B2 Ultra-thin wafer level stack packaging method 有权
标题翻译：超薄晶圆级堆叠封装方法
公开(公告)号：US07192847B2
公开(公告)日：2007-03-20
申请号：US10906136
申请日：2005-02-04
申请人： Min-Chih Hsuan
发明人： Min-Chih Hsuan
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/301 , H01L21/46
CPC分类号： H01L25/50 , H01L23/3114 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.
摘要翻译：提供了一种形成超薄晶片级堆叠封装的方法及其结构。该方法包括提供其上具有多个基底芯片的第一晶片，选择性地将第一晶片连接到第二基板，研磨第一晶片以减小其厚度，切割重叠的第一晶片，将多个堆叠芯片结合到每个基底芯片，以及将基片与封装的堆叠芯片封装形成IC封装。因此，每个IC封装至少包括基片和堆叠片。 IC封装的尺寸几乎与基片相同，厚度稍大于基片和叠片芯片的组合厚度。如果在晶片级封装之前进行基片和堆叠芯片的已知的良好的裸片检查，则IC封装的总产量增加。

8. 发明申请

US20050088517A1 Integrated audio/video sensor 有权
标题翻译：集成音频/视频传感器
公开(公告)号：US20050088517A1
公开(公告)日：2005-04-28
申请号：US10700785
申请日：2003-11-03
申请人： Min-Chih Hsuan
发明人： Min-Chih Hsuan
IPC分类号： H01L29/00 , H04N5/225 , H04N7/18
CPC分类号： H04N5/2254 , H04N5/335
摘要： An integrated audio/video sensor is provided. The integrated sensor comprises an image-receiving module for sensing a light of an image, a sound-receiving module for sensing a sound and a signal-transforming module for integrating image and sound signals into an audio/video signal. The integrated sensor integrates image and sound together simultaneously and synchronously. Furthermore, the integrated sensor can be connected directly to an image-processing system. The integrated sensor not only provides excellent synchronization of audio and video signals, but also reduces the size and cost of producing the integrated sensor as well.
摘要翻译：提供集成的音频/视频传感器。集成传感器包括用于感测图像的光的图像接收模块，用于感测声音的声音接收模块和用于将图像和声音信号集成到音频/视频信号中的信号变换模块。集成传感器将图像和声音同时并入同步。此外，集成传感器可以直接连接到图像处理系统。该集成传感器不仅提供音频和视频信号的卓越同步，而且还降低了生成集成传感器的尺寸和成本。

9. 发明授权

US08976018B2 Local detection processing device and system 有权
标题翻译：本地检测处理设备和系统
公开(公告)号：US08976018B2
公开(公告)日：2015-03-10
申请号：US13431437
申请日：2012-03-27
申请人： Min-Chih Hsuan
发明人： Min-Chih Hsuan
IPC分类号： G08B19/00
CPC分类号： G08B19/00
摘要： A local detection processing system includes a local detection processing device and at least two types of detectors. The detectors are disposed in an area for detecting properties or property changes of a specific target to generate a detection signal. The local detection processing device analyzes the detection signals and transmits the detection result to a processing center. The local detection processing device includes a detection information receiving unit receiving the detection signals generated by the at least two types of detectors; a memory unit recording codes of the at least two types of detectors, a format of the detection signal, information of the corresponding processing center and values of the detection signals; an information processing unit analyzing the received detection signals, determining a detection result whether to transmit the detection result and the processing center; and a communication unit connecting at least two processing centers.
摘要翻译：本地检测处理系统包括本地检测处理装置和至少两种类型的检测器。检测器设置在用于检测特定目标的属性或属性变化的区域中以产生检测信号。本地检测处理装置分析检测信号，并将检测结果发送到处理中心。本地检测处理装置包括：检测信息接收单元，接收由至少两种类型的检测器产生的检测信号; 记录所述至少两种检测器的代码的记录单元，检测信号的格式，相应的处理中心的信息和检测信号的值; 分析接收到的检测信号的信息处理单元，确定是否发送检测结果和处理中心的检测结果; 以及连接至少两个处理中心的通信单元。

10. 发明授权

US08786427B2 Portable information detection and processing device and system 有权
标题翻译：便携式信息检测处理装置及系统
公开(公告)号：US08786427B2
公开(公告)日：2014-07-22
申请号：US13431413
申请日：2012-03-27
申请人： Min-Chih Hsuan
发明人： Min-Chih Hsuan
IPC分类号： G08B1/08
CPC分类号： G08B25/14
摘要： A portable information detection and processing device includes an information detection unit, for detecting information recorded by at least one functional element; a memory unit, for recording recognition data of the at least one functional element and information detected by the functional element; a display unit, for displaying the recognition data of the functional element and the information recorded by the functional element; and an information processing unit, connected to the information detection unit, the memory unit and the display unit, for processing the recognition data of the functional element and the information detected by the functional element, and controlling the information detection unit, the memory unit and the display unit.
摘要翻译：便携式信息检测处理装置包括：信息检测单元，用于检测由至少一个功能元件记录的信息; 用于记录所述至少一个功能元件的识别数据和由所述功能元件检测的信息的存储器单元; 显示单元，用于显示功能元件的识别数据和由功能元件记录的信息; 以及信息处理单元，连接到信息检测单元，存储单元和显示单元，用于处理功能元件的识别数据和由功能元件检测的信息，并且控制信息检测单元，存储单元和显示单元。

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