专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6154801A Verification strategy using external behavior modeling 失效
标题翻译：使用外部行为建模的验证策略
公开(公告)号：US6154801A
公开(公告)日：2000-11-28
申请号：US161342
申请日：1998-09-25
申请人： Mike Lowe , Mark LaVine , Jelena Ilic , Paul Berndt , Tahsin Askar , Enrique Rendon , Hamilton B. Carter
发明人： Mike Lowe , Mark LaVine , Jelena Ilic , Paul Berndt , Tahsin Askar , Enrique Rendon , Hamilton B. Carter
IPC分类号： G06F11/267 , G06F13/40 , G06F17/50 , G06F13/368
CPC分类号： G06F13/4027 , G06F11/221 , G06F17/5022
摘要： A verification system and method for verifying operation of an HDL (Hardware Description Language) design of a computer system component are disclosed. The computer system is configured to interface between a first bus and second bus. During verification, a simulated model of the HDL design is coupled to a simulated first bus and a simulated second bus. A designated stimulus is applied to the simulated model through the simulated first bus. A stimulus file stored in the computer system memory is configured to specify the designated stimulus to be applied. In response to the designated stimulus, the simulated model initiates bus cycles on the simulated second bus. A transaction checker is provided in the computer system memory to receive information relating to these bus cycles from said simulated second bus. By employing two different busses--one to apply a stimulus and the other to resolve the bus cycle through transaction checking--an effective decoupling of test stimulus from the checking environment is achieved. Due to decoupling, the test environment can be made more robust, and can be used to generate random responses, remap memory, inject errors into data streams etc.
摘要翻译：公开了一种用于验证计算机系统组件的HDL（硬件描述语言）设计的操作的验证系统和方法。计算机系统被配置为在第一总线和第二总线之间进行接口。在验证期间，HDL设计的模拟模型耦合到模拟的第一总线和模拟的第二总线。通过模拟的第一条总线将指定的刺激应用于模拟模型。存储在计算机系统存储器中的激励文件被配置为指定要应用的指定的刺激。响应于指定的刺激，模拟模型在模拟的第二总线上启动总线周期。在计算机系统存储器中提供事务检查器，以从所述模拟的第二总线接收与这些总线周期有关的信息。通过使用两个不同的总线 - 一个应用刺激，另一个通过事务检查来解决总线周期 - 实现了测试刺激与检查环境的有效解耦。由于解耦，测试环境可以更加鲁棒，可用于生成随机响应，重映射存储器，将错误注入数据流等。

2. 发明授权

US06173243B2 Memory incoherent verification methodology 失效
标题翻译：记忆不连贯验证方法
公开(公告)号：US06173243B2
公开(公告)日：2001-01-09
申请号：US09161034
申请日：1998-09-25
申请人： Mike Lowe , Mark LaVine , Jelena Ilic , Paul Berndt , Tahsin Askar , Enrique Rendon , Hamilton Carter
发明人： Mike Lowe , Mark LaVine , Jelena Ilic , Paul Berndt , Tahsin Askar , Enrique Rendon , Hamilton Carter
IPC分类号： G06F1300
CPC分类号： G06F13/4027 , G06F11/221 , G06F17/5022
摘要： A system and method for memory incoherent verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design receives a memory read stimulus from a stimulus file through a simulated first bus. The simulated model of the HDL design is configured to send its response to the stimulus onto a simulated second bus. A transaction checker receives the response from the simulated second bus and analyzes it to verify operation of the HDL design of the computer system component. The stimulus file and the transaction checker are both stored in the computer system memory. The simulated model's response to the memory read stimulus is evaluated by the transaction checker independently of any previous memory write stimulus from the stimulus file. There is no need to have a previous memory write operation or a master initialization of the system memory for every memory read operation. This enhances the sequences of operations that may be applied to a device under test. Multiple simulated models may read or write into the memory without timing constraints.
摘要翻译：公开了一种用于计算机系统组件的HDL（硬件描述语言）设计的功能的存储器不相干验证的系统和方法。 HDL设计的模拟模型通过模拟的第一总线从刺激文件接收存储器读取刺激。 HDL设计的模拟模型被配置为将其对刺激的响应发送到模拟的第二总线上。交易检查器从模拟的第二总线接收响应，并对其进行分析，以验证计算机系统组件的HDL设计的操作。刺激文件和事务检查器都存储在计算机系统内存中。模拟模型对存储器读取激励的响应由事务检查器独立于来自刺激文件的任何先前的存储器写入激励来评估。对于每个存储器读操作，不需要先前的存储器写操作或系统存储器的主初始化。这增强了可能应用于被测设备的操作序列。多个模拟模型可以在没有时序限制的情况下读取或写入存储器。

3. 发明授权

US6081864A Dynamic configuration of a device under test 失效
标题翻译：被测设备的动态配置
公开(公告)号：US6081864A
公开(公告)日：2000-06-27
申请号：US161108
申请日：1998-09-25
申请人： Mike Lowe , Paul Berndt , Tahsin Askar , Enrique Rendon
发明人： Mike Lowe , Paul Berndt , Tahsin Askar , Enrique Rendon
IPC分类号： G06F11/267 , G06F13/40 , G06F17/50 , G06F13/00
CPC分类号： G06F13/4027 , G06F11/221 , G06F17/5022
摘要： A system and method for dynamic verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design is created. A test configuration for the simulated model is selected through a configuration interpretation mechanism, based on a plurality of user-supplied parameters. The user-supplied parameters, for example, include the amount of the memory in the system, the number of memory banks, addresses of various PCI devices, the type of the CPU etc. The test configuration is then compiled. At run-time, the test configuration is simulated. The responses by the simulated model of the HDL design to various test stimuli from a stimulus file are then evaluated under the chosen test configuration. One or more different test configurations may be simulated at run-time, and the stimulated model's responses to a pre-determined set of test stimuli may be reevaluated for each such test configuration. Thus, the test configuration is effectively separated from the test stimulus generation mechanism. This allows permutations of a given test suite across many test configurations without creating extremely large number of tests.
摘要翻译：公开了一种用于动态验证计算机系统组件的HDL（硬件描述语言）设计的功能的系统和方法。创建了HDL设计的模拟模型。基于多个用户提供的参数，通过配置解释机制来选择模拟模型的测试配置。例如，用户提供的参数包括系统中的存储器数量，存储体的数量，各种PCI设备的地址，CPU的类型等等。然后对测试配置进行编译。在运行时，模拟测试配置。然后在所选择的测试配置下对HDL设计的模拟模型对刺激文件的各种测试刺激的响应进行评估。可以在运行时模拟一个或多个不同的测试配置，并且可以针对每个这样的测试配置重新评估受刺激模型对预定的一组测试刺激的响应。因此，测试配置与测试刺激产生机制有效分离。这允许给定测试套件在许多测试配置中进行排列，而不会产生极大数量的测试。

4. 发明申请

US20060106962A1 USB On-The-Go implementation 审中-公开
标题翻译： USB On-The-Go实现
公开(公告)号：US20060106962A1
公开(公告)日：2006-05-18
申请号：US10992250
申请日：2004-11-17
申请人： Nancy Woodbridge , Enrique Rendon , Mark Fullerton
发明人： Nancy Woodbridge , Enrique Rendon , Mark Fullerton
IPC分类号： G06F13/42
CPC分类号： G06F13/4291
摘要： In some embodiments a Universal Serial Bus On-The-Go (USB OTG) device includes a USB device controller, a USB host controller, a USB OTG transceiver, and a controller to control a coupling between the USB device controller, the USB host controller, and the USB OTG transceiver, and to control whether the USB device controller, the USB host controller, or a combination of the USB device controller and the USB host controller controls the USB OTG transceiver. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，通用串行总线移动（USB OTG）设备包括USB设备控制器，USB主机控制器，USB OTG收发器和控制器，以控制USB设备控制器，USB主机控制器和USB OTG收发器，并且控制USB设备控制器，USB主机控制器或USB设备控制器和USB主机控制器的组合是否控制USB OTG收发器。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式