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1. 发明公开

US20240395303A1 MEMORY ARRAY WITH COMPENSATED WORD LINE ACCESS DELAY 审中-公开
公开(公告)号：US20240395303A1
公开(公告)日：2024-11-28
申请号：US18794453
申请日：2024-08-05
申请人： Micron Technology, Inc.
发明人： Si Hong Kim , John D. Porter
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/221 , G11C11/2257
摘要： Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

2. 发明公开

US20230420032A1 APPARATUSES AND METHODS FOR INPUT RECEIVER CIRCUITS AND RECEIVER MASKS FOR SAME 审中-公开
公开(公告)号：US20230420032A1
公开(公告)日：2023-12-28
申请号：US18312747
申请日：2023-05-05
申请人： MICRON TECHNOLOGY, INC.
发明人： Dean D. Gans , John D. Porter
IPC分类号： G11C11/4076 , G11C11/4074 , G06F3/06 , G06F13/16
CPC分类号： G11C11/4076 , G11C11/4074 , G06F3/0673 , G06F3/0604 , G06F3/0659 , G06F13/1689
摘要： Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

3. 发明授权

US11646065B2 Wear leveling 有权
公开(公告)号：US11646065B2
公开(公告)日：2023-05-09
申请号：US17367060
申请日：2021-07-02
申请人： Micron Technology, Inc.
发明人： John D. Porter
IPC分类号： G11C7/10 , G06F12/02 , G11C11/22
CPC分类号： G11C7/1042 , G06F12/0246 , G11C7/1039 , G06F2212/7211 , G11C11/221 , G11C2207/2236
摘要： An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

4. 发明授权

US10699755B2 Apparatuses and methods for plate coupled sense amplifiers 有权
公开(公告)号：US10699755B2
公开(公告)日：2020-06-30
申请号：US16134732
申请日：2018-09-18
申请人： MICRON TECHNOLOGY, INC.
发明人： Adam S. El-Mansouri , John D. Porter
IPC分类号： G11C7/06 , G11C11/22 , G11C5/14 , G11C7/22
摘要： Embodiments of the disclosure are drawn to apparatuses and methods for plate coupled sense amplifiers. An example embodiment may include a sense amplifier which may sense a voltage from a memory cell. The sense amplifier may also monitor a change in the voltage, and determine a logical value of the memory cell based on the time when the voltage reaches a trigger voltage. The memory cell may be coupled to a plate with a plate voltage, wherein a change in the plate voltage determines the change of the voltage from the memory cell.

5. 发明授权

US10249358B1 Apparatuses and methods for configurable command and data input circuits for semiconductor memories 有权
公开(公告)号：US10249358B1
公开(公告)日：2019-04-02
申请号：US16190504
申请日：2018-11-14
申请人： MICRON TECHNOLOGY, INC.
发明人： Hyun Yoo Lee , Kang-Yong Kim , John D. Porter
IPC分类号： G11C7/22 , G11C11/4076 , G11C11/4096 , G11C7/10 , G11C11/4074 , G11C11/4093 , G11C11/4091
摘要： Apparatuses and methods for configurable command and data input circuits for semiconductor memories are described. Example apparatuses include input signal blocks, clock blocking circuits, data input blocks, driver circuits, and data receiver circuits.

6. 发明授权

US09054700B2 Apparatus and methods of driving signal for reducing the leakage current 有权
标题翻译：驱动信号以减少漏电流的装置和方法
公开(公告)号：US09054700B2
公开(公告)日：2015-06-09
申请号：US14223647
申请日：2014-03-24
申请人： Micron Technology, Inc.
发明人： Gi-Hong Kim , John D. Porter
IPC分类号： G11C8/00 , G11C11/34 , H03K17/16 , G11C7/10 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/419
CPC分类号： H03K17/162 , G11C7/1057 , G11C7/1096 , G11C7/12 , G11C8/08 , G11C8/10 , G11C11/419
摘要： Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor.
摘要翻译：公开了用于驱动信号的装置和方法。示例性设备包括预驱动器电路和驱动器电路。预驱动器电路包括降压晶体管，并且驱动器电路包括被配置为耦合到参考电压的下拉晶体管。在第一模式中，降压晶体管被配置为将提供给下拉晶体管的电压降低到小于电源电压，并且在第二模式中，降压晶体管被配置为提供电源电压到下拉晶体管。示例性信号驱动器电路的预驱动器电路还可以包括升压晶体管，其被配置为将提供给驱动器电路的上拉晶体管的电压增加到大于参考电压，并且在第二模式中，步骤该晶体管被配置为向上拉晶体管提供参考电压的电压。

7. 发明授权

US12080330B2 Memory array with compensated word line access delay 有权
公开(公告)号：US12080330B2
公开(公告)日：2024-09-03
申请号：US17899859
申请日：2022-08-31
申请人： Micron Technology, Inc.
发明人： Si Hong Kim , John D. Porter
IPC分类号： G11C11/22
CPC分类号： G11C11/2273 , G11C11/221 , G11C11/2257
摘要： Systems and method for sensing an accessed voltage value associated with a memory cell is described. In different embodiments, a memory array may include a different number of sense amplifiers. Moreover, each sense amplifier may include capacitors with different capacitance values to compensate for a difference in received charges associated with a similar memory state caused by various circuit delays. For example, farther memory cells from a word line driver may receive activation signals with higher delays which in turn may result in delayed activation. As such, the sense amplifiers may include capacitors with varying capacitance values to compensate for an amount charge received at a latching time caused by delayed provision of charges associated with the targeted memory states.

8. 发明授权

US11955162B2 Apparatuses and methods for input receiver circuits and receiver masks for same 有权
公开(公告)号：US11955162B2
公开(公告)日：2024-04-09
申请号：US18312747
申请日：2023-05-05
申请人： MICRON TECHNOLOGY, INC.
发明人： Dean D. Gans , John D. Porter
IPC分类号： G06F3/06 , G06F13/16 , G11C11/4074 , G11C11/4076
CPC分类号： G11C11/4076 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F13/1689 , G11C11/4074
摘要： Apparatuses and methods for input receiver circuits and receiver masks for electronic memory are disclosed. Embodiments of the disclosure include memory receiver masks having shapes other than rectangular shapes. For example, a receiver mask according to some embodiments of the disclosure may have a hexagonal shape. Other shapes of receiver masks may also be included in other embodiments of the disclosure. Circuits, timing, and operating parameters for achieving non-rectangular and various shapes of receiver mask are described.

9. 发明申请

US20210383856A1 SENSING A MEMORY CELL 有权
公开(公告)号：US20210383856A1
公开(公告)日：2021-12-09
申请号：US17409608
申请日：2021-08-23
申请人： Micron Technology, Inc.
发明人： Huy T. Vo , Adam S. El-Mansouri , Suryanarayana B. Tatapudi , John D. Porter
IPC分类号： G11C11/22
摘要： Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a first switching component may selectively couple a sense component with the memory cell based on a logic state stored on the memory cell to transfer a charge between the memory cell and the sense component. A second switching component, which may be coupled with the first switching component, may down convert a voltage associated with the charge to another voltage that is within an operation voltage of the sense component. The sense component may operate at a lower voltage than a voltage at which the memory cell operates to reduce power consumption in some cases.

10. 发明授权

US11056157B2 Wear leveling 有权
公开(公告)号：US11056157B2
公开(公告)日：2021-07-06
申请号：US16856562
申请日：2020-04-23
申请人： Micron Technology, Inc.
发明人： John D. Porter
IPC分类号： G11C7/10 , G06F12/02 , G11C11/22
摘要： An apparatus has a controller and an array of memory cells, including a first section comprising a plurality of rows and a second section comprising a plurality of rows. The controller configured to, in association with wear leveling, transfer data stored in a first row of the first section from the first row to a register, transfer the data from the register to a destination row of the second section while data in a second row of the first section is being sensed.

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