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1. 发明授权

US12135600B2 Power management in memory 有权
公开(公告)号：US12135600B2
公开(公告)日：2024-11-05
申请号：US17479922
申请日：2021-09-20
申请人： Micron Technology, Inc.
发明人： Frank F. Ross , Matthew A. Prather
IPC分类号： G06F1/32 , G06F1/3234 , G06F3/06 , G11C5/14
CPC分类号： G06F1/3275 , G06F3/0604 , G06F3/0647 , G06F3/0673 , G11C5/147
摘要： The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

2. 发明公开

US20240096438A1 ERROR DETECTION, CORRECTION, AND MEDIA MANAGEMENT ON A DRAM DEVICE 审中-公开
公开(公告)号：US20240096438A1
公开(公告)日：2024-03-21
申请号：US18169610
申请日：2023-02-15
申请人： Micron Technology, Inc.
发明人： Amitava Majumdar , Greg S. Hendrix , Anandhavel Nagendrakumar , Krunal Patel , Kirthi Shenoy , Danilo Caraccio , Ankush Lal , Frank F. Ross , Adam D. Gailey
IPC分类号： G11C29/52 , G11C29/00
CPC分类号： G11C29/52 , G11C29/76 , G11C29/789
摘要： In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.

3. 发明授权

US11740797B2 Non-deterministic memory protocol 有权
公开(公告)号：US11740797B2
公开(公告)日：2023-08-29
申请号：US17893118
申请日：2022-08-22
申请人： Micron Technology, Inc.
发明人： Robert M. Walker , James A. Hall, Jr. , Frank F. Ross
IPC分类号： G06F3/06 , G06F12/00 , G06F12/02 , G06F13/16
CPC分类号： G06F3/061 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F12/00 , G06F12/0246 , G06F13/1626 , G06F2212/1024 , G06F2212/7203 , G06F2212/7208
摘要： The present disclosure includes apparatuses and methods related to a non-deterministic memory protocol. An example apparatus can perform operations on the memory device based on commands received from a host according to a protocol, wherein the protocol includes non-deterministic timing of the operations. The memory device can be a non-volatile dual in-line memory module (NVDIMM) device.

4. 发明申请

US20220229791A1 METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 有权
公开(公告)号：US20220229791A1
公开(公告)日：2022-07-21
申请号：US17712006
申请日：2022-04-01
申请人： Micron Technology, Inc.
发明人： Matthew A. Prather , Frank F. Ross , Randall J. Rooney
IPC分类号： G06F13/16 , G11C11/406 , G11C7/22 , G06F3/06 , G06F13/40
摘要： Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.

5. 发明申请

US20220214600A1 COMMAND BUS IN MEMORY 有权
公开(公告)号：US20220214600A1
公开(公告)日：2022-07-07
申请号：US17700187
申请日：2022-03-21
申请人： Micron Technology, Inc.
发明人： Frank F. Ross , Matthew A. Prather
IPC分类号： G03B11/04 , G03B17/12 , H04N5/225 , G06V10/147
摘要： The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

6. 发明授权

US11301403B2 Command bus in memory 有权
公开(公告)号：US11301403B2
公开(公告)日：2022-04-12
申请号：US16289967
申请日：2019-03-01
申请人： Micron Technology, Inc.
发明人： Frank F. Ross , Matthew A. Prather
IPC分类号： G06F13/16 , G06F3/06 , G11C5/04
摘要： The present disclosure includes apparatuses and methods related to a command bus in memory. A memory module may be equipped with multiple memory media types that are responsive to perform various operations in response to a common command. The operations may be carried out during the same clock cycle in response to the command. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices each coupled to the first number of memory devices via a second number of ports, wherein the second number of memory devices each include a controller, and wherein the first number of memory devices and the second number of memory devices can receive a command from the host to perform the various (e.g., the same or different) operations, sometime concurrently.

7. 发明申请

US20210382662A1 ADDRESSING IN MEMORY WITH A READ IDENTIFICATION (RID) NUMBER 有权
公开(公告)号：US20210382662A1
公开(公告)日：2021-12-09
申请号：US17409212
申请日：2021-08-23
申请人： Micron Technology, Inc.
发明人： Frank F. Ross
IPC分类号： G06F3/06 , G06F13/16 , G06F12/0868
摘要： The present disclosure includes apparatuses and methods related to a memory apparatus and/or method for addressing in memory with a read identification (RID) number. An example apparatus can include a first memory device, a second memory device coupled to the first memory device, and a controller coupled to the first memory device and the second memory device, wherein the controller is configured to receive a read command requesting data from the first memory device, wherein the read command includes a read identification (RID) number that includes an address to identify a location of the data in the first memory device, and transfer the data from the location in the first memory device to the second memory device in response receiving the read command.

8. 发明授权

US11163487B2 Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same 有权
公开(公告)号：US11163487B2
公开(公告)日：2021-11-02
申请号：US16029269
申请日：2018-07-06
申请人： Micron Technology, Inc.
发明人： Frank F. Ross
IPC分类号： G06F3/06 , G11C11/4093
摘要： Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a memory device can asynchronously indicate to a connected host that information in a mode register has been changed, obviating the need for repeated polling of the information and thereby reducing both command/address bus and data bus bandwidth consumption. In one embodiment, a memory device comprises a memory; a mode register storing information corresponding to the memory; and circuitry configured to, in response to the information in the mode register being modified by the memory device, generate a notification to a connected host device.

9. 发明授权

US11126251B2 Power management in memory 有权
公开(公告)号：US11126251B2
公开(公告)日：2021-09-21
申请号：US16290181
申请日：2019-03-01
申请人： Micron Technology, Inc.
发明人： Frank F. Ross , Matthew A. Prather
IPC分类号： G06F1/32 , G06F1/3234 , G11C5/14 , G06F3/06
摘要： The present disclosure includes apparatuses and methods related to power management in memory. Memory devices with multiple input/output ports may have the ports separately managed to transfer data from the various to a host or other components of the module based on certain power management signaling or constraints. For example, a memory device with multiple ports may be managed to transfer data to a host from one set of ports in response to power management (or other) signaling, and the device may be managed to transfer other data to another memory device in response to different power management (or other signaling). Power management may be done onboard a memory module with or without direction from a host. Power management may be performed by a dedicated integrated circuit. Data may be transferred from or between different classes of memory devices, using different ports, based on power management, e.g., criteria.

10. 发明申请

US20210255779A1 DUAL SPEED MEMORY 有权
公开(公告)号：US20210255779A1
公开(公告)日：2021-08-19
申请号：US17313860
申请日：2021-05-06
申请人： Micron Technology, Inc.
发明人： Frank F. Ross , Matthew A. Prather
IPC分类号： G06F3/06 , G06F13/16
摘要： The present disclosure includes apparatuses and methods related to dual speed memory. A memory module can include a number of memory devices that coupled to a host via a number of first ports and coupled to a controller via a number of second ports. The memory module can be configured to transfer data on the first number of ports at a first clock speed and transfer data on the second number of ports at a second clock speed. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports, and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein the first number of memory devices are configured to transfer data between the first number of memory devices and the host at a first clock speed via the first number of ports and the second number of memory devices are configured to transfer data between the first number of memory devices and the second number of memory devices at a second clock speed via the second number of ports.

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