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    • 1. 发明授权
    • Polling control system for switching units in a plural stage switching
matrix
    • 多级切换矩阵中切换单元的轮询控制系统
    • US5276445A
    • 1994-01-04
    • US798698
    • 1991-11-26
    • Michio MitaKimiyasu SatoHidetoshi Nishimoto
    • Michio MitaKimiyasu SatoHidetoshi Nishimoto
    • G11B27/024G11B27/028G11B27/34G11B27/36H04H60/04H04N5/268H04Q1/00
    • G11B27/34G11B27/028G11B27/36H04N5/268G11B2220/90G11B27/024H04H60/04
    • A matrix switching apparatus includes a plurality of switching units connected in tandem, each switching unit having a plurality of input terminals and a plurality of output terminals. There are a plurality of transmission/reception units, each provided within a respective switching unit and also within a remote control unit. The transmission/reception units are for transmitting switching data. A first one of the transmission/reception units is set to a master station mode and sequentially polls the remaining transmission/reception units which are set to a slave station mode. The remaining units respond to the polling by outputting switching data, which is collectively transmitted by the master station over a serial busline. The remaining transmission/reception units receive only relevant data from the switching data transmitted over the serial busline and supply the relevant data to controlling units which control the turning on and off of crosspoint switches in the switching units.
    • 矩阵切换装置包括多个串联连接的开关单元,每个开关单元具有多个输入端子和多个输出端子。 存在多个发送/接收单元,每个发送/接收单元设置在相应的开关单元内并且还设置在远程控制单元内。 发送/接收单元用于发送切换数据。 发送/接收单元中的第一个被设置为主站模式,并且顺序地轮询设置为从站模式的剩余发送/接收单元。 其余单元通过输出由主站通过串行总线传输的切换数据来响应轮询。 剩余的发送/接收单元仅接收通过串行总线发送的切换数据的相关数据,并将相关数据提供给控制交换单元中交叉点开关的导通和关断的控制单元。
    • 7. 发明授权
    • Data correction circuit
    • 数据校正电路
    • US4360841A
    • 1982-11-23
    • US220094
    • 1980-12-24
    • Michio Mita
    • Michio Mita
    • G11B20/18G11B27/024G11B27/10G11B27/32G11B27/02G11B15/18
    • G11B27/024G11B20/18G11B27/107G11B27/323G11B2220/90
    • A time code correction circuit is formed of an input circuit for receiving an input time code; first and second memories for storing data representing the time code; an adder for selectively incrementing or decrementing data to be supplied to the first and second memories; a comparator comparing the data stored in the first memory with the input time code; a switch controlled by the comparator for selectively supplying the adder with the input time code and the data started second memory; and an output circuit coupled to provide the contents of the second memory as a corrected output time code. Where the time code is reproduced from a time code track recorded on a magnetic tape, the correction circuit is favorably adapted to produce a continuous time code sequence despite dropout in the recorded time code. Also, if a jump occurs in the recorded time code sequence, the correction circuit causes the output time code to reflect such jump with a minimum of signal disturbance.
    • 时间码校正电路由用于接收输入时间码的输入电路形成; 用于存储表示时间码的数据的第一和第二存储器; 用于选择性地递增或递减要提供给第一和第二存储器的数据的加法器; 将存储在第一存储器中的数据与输入时间码进行比较的比较器; 由比较器控制的开关,用于选择性地向加法器提供输入时间码和数据开始的第二存储器; 以及输出电路,被耦合以提供第二存储器的内容作为校正的输出时间码。 在从记录在磁带上的时间码轨道再现时间码的情况下,校正电路有利地适于产生连续的时间码序列,尽管在记录的时间码中出现了丢失。 此外,如果在记录的时间码序列中发生跳转,则校正电路使得输出时间码以最小的信号干扰来反映这种跳跃。