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1. 发明授权

US07026252B2 Etching aftertreatment method 失效
标题翻译：蚀刻后处理方法
公开(公告)号：US07026252B2
公开(公告)日：2006-04-11
申请号：US10372271
申请日：2003-02-25
申请人： Michinobu Mizumura , Ryouji Fukuyama , Mamoru Yakushiji , Yutaka Ohmoto , Katsuya Watanabe
发明人： Michinobu Mizumura , Ryouji Fukuyama , Mamoru Yakushiji , Yutaka Ohmoto , Katsuya Watanabe
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/31138 , H01L21/76802
摘要： After etching a Si-containing low permittivity insulating film with chlorine based gas, the etched wafer is subjected to an etching aftertreatment process comprising introducing oxygen gas to a vacuum processing chamber with a pressure as low as 0.2 Pa to 1 Pa and a flow rate as low as 5 cc to 20 cc/min, generating plasma within the chamber, heating the wafer 2 being subjected to aftertreatment between 50° C. and 200° C., applying a wafer bias power within the range of 50 W to 200 W, and exposing the wafer to the generated plasma, thereby simultaneously removing the photoresist components, the antireflection film components and the halogen components.
摘要翻译：在用含氯气体蚀刻含Si低介电常数绝缘膜之后，对经蚀刻的晶片进行蚀刻后处理，其中包括将氧气引入至低至0.2Pa至1Pa的压力的真空处理室中，流速为低至5cc至20cc / min，在室内产生等离子体，加热晶片2在50℃和200℃之间进行后处理，将晶片偏置功率施加在50W至200W的范围内，并将晶片暴露于产生的等离子体，从而同时去除光致抗蚀剂组分，抗反射膜组分和卤素组分。

2. 发明授权

US07122479B2 Etching processing method 失效
标题翻译：蚀刻加工方法
公开(公告)号：US07122479B2
公开(公告)日：2006-10-17
申请号：US10228917
申请日：2002-08-28
申请人： Yutaka Ohmoto , Ryouji Fukuyama , Mamoru Yakushiji , Michinobu Mizumura
发明人： Yutaka Ohmoto , Ryouji Fukuyama , Mamoru Yakushiji , Michinobu Mizumura
IPC分类号： H01L21/302
CPC分类号： H01J37/32082 , H01J2237/3342 , H01L21/31116 , H01L21/31138
摘要： An etching processing method capable of etching a low dielectric constant layer at a reduced cost by using an etching processing apparatus comprising a vacuum vessel, a sample loading electrode disposed in the vacuum vessel, a gas introduction device for introducing a reaction gas into the vacuum vessel, an antenna for forming plasmas in the vacuum vessel, and a high frequency power supply for supplying a bias power to a sample loaded on the sample loading electrode, wherein the bias power to be supplied to the sample is 3 W/cm2 or less, and the gas introduction device introduces a gas containing chlorine atoms or bromine atoms to apply etching processing to an inorganic insulation material of low dielectric constant loaded on the loading electrode.
摘要翻译：一种蚀刻处理方法，其能够通过使用包括真空容器，设置在真空容器中的样品加载电极的蚀刻处理装置，以较低的成本蚀刻低介电常数层，将反应气体引入真空容器中的气体引入装置，用于在真空容器中形成等离子体的天线和用于向装载在样本加载电极上的样品提供偏置功率的高频电源，其中待提供给样品的偏置功率为3W / 2以下，气体引入装置引入含有氯原子或溴原子的气体，对负载在负载电极上的低介电常数的无机绝缘材料进行蚀刻处理。

3. 发明授权

US07009714B2 Method of dry etching a sample and dry etching system 失效
标题翻译：干法蚀刻样品和干蚀刻系统的方法
公开(公告)号：US07009714B2
公开(公告)日：2006-03-07
申请号：US10372838
申请日：2003-02-26
申请人： Yutaka Ohmoto , Ryouji Fukuyama , Mamoru Yakushiji
发明人： Yutaka Ohmoto , Ryouji Fukuyama , Mamoru Yakushiji
IPC分类号： G01B9/02
CPC分类号： H01L21/31138 , G01B11/0625 , G01B11/0683 , G01N21/4788 , G01N21/9501 , H01L21/67069
摘要： A process recipe is controlled by processing reflection interference light on the surface of a wafer with a signal and etching is carried out by suppressing an increase in the surface roughness of the wafer during etching. That is, a dry etching method for use in a dry etching system comprising means of treating a sample by generating plasma in a vacuum process chamber and monitor means of monitoring the reflection interference light of the sample to be treated, the method comprising the step of detecting the spectrum of reflection interference light on the surface of the sample to be treated, the step of obtaining a residual from curve fit between a theoretical value estimated from the film reflection model of the surface of the wafer and the spectrum of reflection interference light, and the step of judging whether the residual from the curve fit falls within a predetermined value.
摘要翻译：通过用信号处理晶片表面上的反射干涉光来控制工艺配方，并且通过抑制蚀刻期间晶片的表面粗糙度的增加来进行蚀刻。也就是说，干蚀刻系统中使用的干法蚀刻方法，包括在真空处理室中产生等离子体处理样品和监测待处理样品的反射干涉光的监测装置的方法，该方法包括以下步骤：检测待处理样品的表面上的反射干涉光的光谱，从由晶片表面的膜反射模型估计出的理论值与反射干涉光的光谱之间的曲线拟合的残差获得的步骤，以及判断曲线拟合的残差是否落在预定值内的步骤。

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