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1. 发明授权

US5862099A Non-volatile programmable memory having a buffering capability and method of operation thereof 失效
标题翻译：具有缓冲能力的非易失性可编程存储器及其操作方法
公开(公告)号：US5862099A
公开(公告)日：1999-01-19
申请号：US939785
申请日：1997-09-29
申请人： Michel E. Gannage , David K. Wong , Asim A. Bajwa
发明人： Michel E. Gannage , David K. Wong , Asim A. Bajwa
IPC分类号： G11C7/00 , G11C16/10
CPC分类号： G11C16/10 , G11C7/00
摘要： A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustratively a serial device connected to the serial port of the microcontroller. The memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessible to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.
摘要翻译：计算机系统包括诸如微控制器和存储器设备的计算设备。存储器件例如是连接到微控制器的串行端口的串行设备。存储器件包括页锁存器负载电路，其向微控制器提供串行I / O并且以预定顺序向/从页锁存器传送I / O位。页锁存器通过许多位线连接到存储单元阵列。该页面锁存器不仅支持对存储单元阵列中的扇区进行编程和读取，而且还提供以下功能中的一个或多个：微控制器可直接作为SRAM临时存储器访问，可直接从存储单元阵列加载，以方便单字节 “读 - 修改 - 写”操作，并可在编程操作期间加载以支持实时应用程序。

2. 发明授权

US5724303A Non-volatile programmable memory having an SRAM capability 失效
标题翻译：具有SRAM能力的非易失性可编程存储器
公开(公告)号：US5724303A
公开(公告)日：1998-03-03
申请号：US601963
申请日：1996-02-15
申请人： Michael E. Gannage , David K. Wong , Asim A. Bajwa
发明人： Michael E. Gannage , David K. Wong , Asim A. Bajwa
IPC分类号： G11C7/00 , G11C16/10
CPC分类号： G11C16/10 , G11C7/00
摘要： A computer system includes a computing device such as a microcontroller and a memory device. The memory device is illustrtively a serial device connected to the serail port of the microcontrollerThe memory device includes a page latch load circuit which provides serial I/O to the microcontroller and transfers I/O bits in a predetermined order to/from the page latches. Page latches are connected over many bit lines to a memory cell array. The page latches not only supports programming and reading of sectors in the memory cell array, but also provides one or more of the following functions: directly accessable to the microcontroller as an SRAM scratch pad, directly loadable from the memory cell array to facilitate single byte "read-modify-write" operations, and loadable during programming operations to support real time applications.
摘要翻译：计算机系统包括诸如微控制器和存储器设备的计算设备。该存储器装置是连接到微控制器的串行端口的串行设备。存储器件包括一个页锁存器负载电路，其向微控制器提供串行I / O并且以预定顺序向/从页锁存器传送I / O位。页锁存器通过许多位线连接到存储单元阵列。页面锁存器不仅支持对存储单元阵列中的扇区进行编程和读取，而且还提供以下一个或多个功能：可直接作为SRAM暂存器访问微控制器，可从存储单元阵列直接加载以便于单字节 “读 - 修改 - 写”操作，并可在编程操作期间加载以支持实时应用程序。

3. 发明授权

US5991194A Method and apparatus for providing accessible device information in digital memory devices 失效
标题翻译：用于在数字存储设备中提供可访问设备信息的方法和装置
公开(公告)号：US5991194A
公开(公告)日：1999-11-23
申请号：US957094
申请日：1997-10-24
申请人： Robin J. Jigour , Asim A. Bajwa
发明人： Robin J. Jigour , Asim A. Bajwa
IPC分类号： G11C5/00 , G11C16/20 , G11C16/22 , G11C16/04 , G11C8/00
CPC分类号： G11C5/06 , G11C16/20 , G11C16/22
摘要： A memory device (100) includes a user device information sector (122) in addition to normal sectors (124) of a memory array. The user device information sector includes a product identification field (240) and a restricted address list field (250), and optionally includes a customer identification number field (220) and a serial number field (230). The product identification field includes such information as the manufacturer ID, a part number ID, package/speed identification, temperature/voltage identification, and byte locations for special options. The device identification field is factory programmed using a high voltage enabling signal applied to a write control logic circuit (102) in the memory device in conjunction with a "Device Information Sector Program" instruction is applied to the SPI command and control logic (110). The device information sector is read from the application using a "Read Device Information" instruction. Inadvertent corruption of the device information sector is avoided since a high voltage typically is not available in the application, and the "Device Information Sector Program" instruction is not in the application command set.
摘要翻译：除了存储器阵列的正常扇区（124）之外，存储器设备（100）还包括用户设备信息扇区（122）。用户设备信息扇区包括产品识别字段（240）和受限地址列表字段（250），并且可选地包括客户标识号字段（220）和序列号字段（230）。产品识别字段包括制造商ID，部件号，封装/速度识别，温度/电压识别和特殊选项的字节位置等信息。结合“SPI设备信息扇区程序”指令应用于SPI命令和控制逻辑（110）的设备识别字段是使用施加到存储器件中的写入控制逻辑电路（102）的高电压使能信号进行工厂编程的，。使用“读取设备信息”指令从应用程序读取设备信息扇区。避免了设备信息扇区的意外损坏，因为高电压通常在应用中不可用，并且“设备信息扇区程序”指令不在应用程序命令集中。

4. 发明授权

US06861895B1 High voltage regulation circuit to minimize voltage overshoot 有权
标题翻译：高电压调节电路，以最大限度地减少电压过冲
公开(公告)号：US06861895B1
公开(公告)日：2005-03-01
申请号：US10464129
申请日：2003-06-17
申请人： Ping-Chen Liu , Asim A. Bajwa
发明人： Ping-Chen Liu , Asim A. Bajwa
IPC分类号： H01L27/08 , H02M3/07 , G05F3/02
CPC分类号： H01L27/0802 , H02M3/073
摘要： A resistive divider for a voltage multiplier circuit minimizes output voltage overshoot by capacitively coupling the tap point of the resistive divider to the output terminal of the voltage multiplier circuit via the parasitic capacitance of the resistive divider. For a resistive divider that includes a resistive structure formed over a dielectric layer formed on a doped well, this capacitive coupling can be performed by connecting the well to the output terminal of the voltage multiplier circuit. This capacitive coupling improves the response time of the resistive divider, so that a scaled test voltage read from the tap point varies more rapidly than the elevated output voltage of the voltage multiplier circuit. Therefore, the scaled test voltage provides charging control that increases the elevated output voltage in gradual increments that prevent the elevated output voltage from exceeding a target output voltage.
摘要翻译：用于电压倍增器电路的电阻分压器通过电阻分压器的抽头点通过电阻分压器的寄生电容电容耦合到电压倍增器电路的输出端来最小化输出电压过冲。对于包括在形成于掺杂阱上的电介质层上形成的电阻结构的电阻分压器，可以通过将阱连接到电压倍增器电路的输出端来执行该电容耦合。这种电容耦合提高了电阻分压器的响应时间，从而从分接点读取的经缩放的测试电压比电压倍增器电路的升高的输出电压更快地变化。因此，缩放的测试电压提供充电控制，其以逐渐增加的方式增加升高的输出电压，从而防止升高的输出电压超过目标输出电压。

5. 发明授权

US07088627B1 Column redundancy scheme for non-volatile flash memory using JTAG input protocol 有权
标题翻译：使用JTAG输入协议的非易失性闪存的列冗余方案
公开(公告)号：US07088627B1
公开(公告)日：2006-08-08
申请号：US10629365
申请日：2003-07-29
申请人： Asim A. Bajwa , Ping-Chen Liu
发明人： Asim A. Bajwa , Ping-Chen Liu
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C29/82 , G11C29/824 , G11C2216/14 , G11C2216/30
摘要： A JTAG-programmable IC includes a memory array having redundant columns, a partial-width data register, and a full-width bitline register. A programming bitstream is shifted into the data register in discrete portions, with each portion being loaded into the bitline latch before the next portion is shifted into the data register. The programming bitstream portions fill the bitline latch sequentially unless a count indicator for a particular portion matches a predetermined defective column value, in which case that bitstream portion is rerouted to a region of the bitline latch associated with the redundant columns of the memory array. The count indicator is incremented with each new bitstream portion shifted into the data register. Once the programming bitstream is fully loaded into the bitline latch, the data is programmed into a selected row of the memory array in page mode.
摘要翻译： JTAG可编程IC包括具有冗余列的存储器阵列，部分宽度数据寄存器和全宽位线寄存器。编程比特流以离散部分移入数据寄存器，每个部分在下一部分移入数据寄存器之前被加载到位线锁存器中。编程比特流部分顺序填充位线锁存器，除非特定部分的计数指示符与预定的缺陷列值匹配，在这种情况下，比特流部分被重新路由到与存储器阵列的冗余列相关联的位线锁存器的区域。每个新的比特流部分移入数据寄存器中，计数指示符递增。一旦编程比特流被完全加载到位线锁存器中，则以页面模式将数据编程到存储器阵列的选定行中。

6. 发明授权

US06816420B1 Column redundancy scheme for serially programmable integrated circuits 有权
标题翻译：串行可编程集成电路的列冗余方案
公开(公告)号：US06816420B1
公开(公告)日：2004-11-09
申请号：US10629109
申请日：2003-07-29
申请人： Ping-Chen Liu , Asim A. Bajwa
发明人： Ping-Chen Liu , Asim A. Bajwa
IPC分类号： G11C700
CPC分类号： G11C29/848 , G11C29/846 , G11C29/86 , G11C2216/30
摘要： A serially programmable integrated circuit (IC) includes a memory array and multiple data registers daisy-chained by bypass logic. Each of the data registers is associated with a primary column grouping or redundant column grouping in the memory array. If a data register is associated with a primary column grouping that includes a defective column, the bypass logic bypasses that data register and incorporates one of the data registers associated with a redundant column grouping into the serial programming path of the IC. Therefore, when a programming bitstream is shifted into this serial programming path, defective columns in the memory array are automatically bypassed during the subsequent programming operation. To read a word from the memory array, any data stored in the redundant columns is first read out, and then the data from the primary columns is read out, bypassing the previously identified defective column groupings.

7. 发明授权

US5313429A Memory circuit with pumped voltage for erase and program operations 失效
标题翻译：具有抽取电压的存储器电路用于擦除和编程操作
公开(公告)号：US5313429A
公开(公告)日：1994-05-17
申请号：US837303
申请日：1992-02-14
申请人： Christophe J. Chevallier , Asim A. Bajwa , Darrell D. Rinerson , Steve K. Hsia
发明人： Christophe J. Chevallier , Asim A. Bajwa , Darrell D. Rinerson , Steve K. Hsia
IPC分类号： G11C5/14 , G11C16/30 , G11C16/02
CPC分类号： G11C5/145 , G11C16/30
摘要： A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memory device includes a charge pump section that internally generates the high voltage required for programming and erase operations. The same charge pump section is used for both program and erase power requirements.
摘要翻译：公开了一种采用热电子注入进行编程操作和Fowler-Nordheim隧道进行擦除操作的存储器件。存储器件只需要一个5伏电源，不需要外部高电压电源进行编程或擦除操作。存储器件包括电荷泵部分，其在内部产生编程和擦除操作所需的高电压。同样的电荷泵部分用于编程和擦除电源要求。

8. 发明授权

US5216588A Charge pump with high output current 失效
标题翻译：高输出电流的电荷泵
公开(公告)号：US5216588A
公开(公告)日：1993-06-01
申请号：US837172
申请日：1992-02-14
申请人： Asim A. Bajwa , Christophe J. Chevallier
发明人： Asim A. Bajwa , Christophe J. Chevallier
IPC分类号： H02M3/07
CPC分类号： H02M3/07
摘要： A charge pump circuit is disclosed that enables the conversion of a low voltage to a higher voltage while delivering a substantial amount of current. The charge pump circuit includes a plurality of diode-capacitor voltage multiplier pump units connected in parallel with respect to each other. The plurality of pump units are switched at different times during the pump frequency to minimize noise generation. In one embodiment, the charge pump circuit is capable of delivering 8 mA of current.
摘要翻译：公开了一种电荷泵电路，其能够在输送大量电流的同时将低电压转换为较高电压。电荷泵电路包括相对于彼此并联连接的多个二极管 - 电容器电压倍增器泵单元。在泵频率期间，多个泵单元在不同时间被切换以最小化噪声产生。在一个实施例中，电荷泵电路能够传送8mA的电流。

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