专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07222326B2 Automatic process and design method, system and program product 有权
标题翻译：自动过程和设计方法，系统和程序产品
公开(公告)号：US07222326B2
公开(公告)日：2007-05-22
申请号：US10709130
申请日：2004-04-15
申请人： Michel E. Bohn , Pierre J. Bouchard , Neil O. Ginter , Derrick J. Kunze , Reginald H. Vance
发明人： Michel E. Bohn , Pierre J. Bouchard , Neil O. Ginter , Derrick J. Kunze , Reginald H. Vance
IPC分类号： G06F17/50
CPC分类号： G05B19/4183 , G05B2219/32129 , G05B2219/35032 , G05B2219/45031 , H01L21/78 , Y02P90/10 , Y02P90/265
摘要： A method, system and program product for generating a process aid on a wafer are disclosed. A “process aid” can be any device provided on a wafer that assists in some process step, but does not ultimately make up part of a usable die. The invention implements libraries of technology design rules, and process aid parameters, and a process aid instruction file library to allow automatic generation of a process aid according to the technology design rules and parameters. As a result, all the inputs required to build a process aid are available up front, which allows the invention to automatically adjust kerf designs to conform to the new technologies. In addition, the invention provides documentation indicating the inputs and details of the process aid produced.
摘要翻译：公开了一种用于在晶片上产生加工助剂的方法，系统和程序产品。 “加工助剂”可以是提供在晶片上的任何装置，其有助于一些工艺步骤，但是最终不能构成可用的模具的一部分。本发明实现了技术设计规则库和处理辅助参数，以及一个可以根据技术设计规则和参数自动生成过程辅助的过程辅助指令文件库。因此，建立加工助剂所需的所有投入都可以在前面获得，这使得本发明可以自动调整切口设计以符合新技术。此外，本发明提供了指出所生产的加工助剂的输入和细节的文件。

2. 发明授权

US07089138B1 Canary device for failure analysis 失效
标题翻译：金丝雀装置进行故障分析
公开(公告)号：US07089138B1
公开(公告)日：2006-08-08
申请号：US10906590
申请日：2005-02-25
申请人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
发明人： Pierre J. Bouchard , Mark C. Hakey , Mark E. Masters , Leah M. P. Pastel , James A. Slinkman , David P. Vallett
IPC分类号： G06F11/00
CPC分类号： G01R31/2856 , G01R31/2831 , G01R31/318511 , G01R31/3187
摘要： A diagnostic system and method for testing an integrated circuit during fabrication thereof. The diagnostic system has at least one integrated circuit chip that has an electrical signature associated with it; a sacrificial circuit that is adjacent to the integrated circuit chip and has a known electrical signature associated with it and intentionally mis-designed circuitry; and a comparator adapted to compare the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit, wherein a match in the electrical signature of the integrated circuit chip with the known electrical signature of the sacrificial circuit indicates that the integrated circuit chip is mis-designed. The diagnostic system further includes a semiconductor wafer that has a plurality of integrated circuit chips and a kerf area separating one integrated circuit chip from another integrated circuit chip. A mis-designed integrated circuit chip has abnormally functioning circuitry.
摘要翻译：一种在其制造期间测试集成电路的诊断系统和方法。诊断系统具有至少一个具有与其相关联的电特征的集成电路芯片; 牺牲电路，其与集成电路芯片相邻并且具有与其相关联的已知电气签名和故意错误设计的电路; 以及比较器，用于将集成电路芯片的电特征与牺牲电路的已知电特征进行比较，其中集成电路芯片的电特征中与牺牲电路的已知电气签名的匹配指示集成电路芯片设计错误。诊断系统还包括具有多个集成电路芯片的半导体晶片和将一个集成电路芯片与另一个集成电路芯片分离的切口区域。错误设计的集成电路芯片具有异常功能的电路。

3. 发明授权

US08495525B1 Lithographic error reduction by pattern matching 失效
标题翻译：通过图案匹配减少平版印刷误差
公开(公告)号：US08495525B1
公开(公告)日：2013-07-23
申请号：US13424816
申请日：2012-03-20
申请人： Aditya Chaudhary , Pierre J. Bouchard , Kalpesh G. Dave
发明人： Aditya Chaudhary , Pierre J. Bouchard , Kalpesh G. Dave
IPC分类号： G06F17/50
CPC分类号： G03F1/44 , G03F1/36
摘要： A library of waivable images with corresponding waiver constraints is generated. Each of the waivable images is an image of a region of a reference design layout including a raw error as determined by an optical rule checks (ORC) program and does not require a correction for printability on a photoresist layer. A list of raw errors is generated by running the ORC program on a target design layout. Error region images corresponding to the list of raw errors are generated by selecting a region of the target design layout around points corresponding to the raw errors. A list of matches between the library of waivable images and the error region images is generated. By removing a subset of raw errors that correspond to a subset of the list of matches from the list of raw errors, a list of real errors is generated.
摘要翻译：生成具有相应豁免约束的可放置图像库。每个可放弃的图像是包括由光学规则检查（ORC）程序确定的原始错误的参考设计布局的区域的图像，并且不需要对光致抗蚀剂层上的可印刷性进行校正。通过在目标设计布局上运行ORC程序来生成原始错误列表。通过在与原始错误对应的点周围选择目标设计布局的区域来生成与原始错误列表相对应的错误区域图像。生成可放映图像库和错误区域图像之间的匹配列表。通过从原始错误列表中删除与匹配列表的子集相对应的原始错误的子集，生成实际错误的列表。

4. 发明授权

US07448017B2 System and method of automatically generating kerf design data 失效
标题翻译：自动生成切口设计数据的系统和方法
公开(公告)号：US07448017B2
公开(公告)日：2008-11-04
申请号：US11763808
申请日：2007-06-15
申请人： Howard T. Barrett , Pierre J. Bouchard , James B. Clairmont , Karen S. Edwards , Maureen F. McFadden , John F. Rudden, Jr. , Florence Marie St. Pierre Sears , Jeffrey C. Stamm
发明人： Howard T. Barrett , Pierre J. Bouchard , James B. Clairmont , Karen S. Edwards , Maureen F. McFadden , John F. Rudden, Jr. , Florence Marie St. Pierre Sears , Jeffrey C. Stamm
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5068
摘要： A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.
摘要翻译：提供了一种方法和系统，以对芯片设计和切角设计采用相同的设计操作过程。并口生成切口设计和芯片设计提供了一致，准确和可重复的过程。由于切片中的数据与芯片中的数据匹配，因此提高了晶圆测试的质量。掩模制造的总循环时间减少，因为在开始掩模制造过程之前完成切口构造。还提供了在切割和芯片设计期间跨多个服务器的负载平衡的使用，以优化计算资源。

5. 发明授权

US07275234B2 System and method of automatically generating kerf design data 失效
标题翻译：自动生成切口设计数据的系统和方法
公开(公告)号：US07275234B2
公开(公告)日：2007-09-25
申请号：US10605109
申请日：2003-09-09
申请人： Howard T. Barrett , Pierre J. Bouchard , James B. Clairmont , Karen S. Edwards , Maureen F. McFadden , John F. Rudden, Jr. , Florence Marie St. Pierre Sears , Jeffrey C. Stamm
发明人： Howard T. Barrett , Pierre J. Bouchard , James B. Clairmont , Karen S. Edwards , Maureen F. McFadden , John F. Rudden, Jr. , Florence Marie St. Pierre Sears , Jeffrey C. Stamm
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5068
摘要： A method and system is provided to use the same design manipulation processes for both chip design and kerf design. Concurrent generation of kerf designs and chip designs provides a consistent, accurate, and repeatable process. Improved quality of wafer testing results because the data in the kerf matches data in the chip. The total cycle time for mask manufacturing is reduced because kerf build is accomplished prior to start of the mask manufacturing process. Also provided is the use of load balancing across multiple servers during kerf and chip design to optimize computing resources.
摘要翻译：提供了一种方法和系统，以对芯片设计和切角设计采用相同的设计操作过程。并口生成切口设计和芯片设计提供了一致，准确和可重复的过程。由于切片中的数据与芯片中的数据匹配，因此提高了晶圆测试的质量。掩模制造的总循环时间减少，因为在开始掩模制造过程之前完成切口构造。还提供了在切割和芯片设计期间跨多个服务器的负载平衡的使用，以优化计算资源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式