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1. 发明申请

US20050230841A1 Integrated circuit package with low modulus layer and capacitor/interposer 失效
标题翻译：集成电路封装，具有低模量层和电容/内插器
公开(公告)号：US20050230841A1
公开(公告)日：2005-10-20
申请号：US10825400
申请日：2004-04-15
申请人： Michael Walk , Hamid Azimi , John Guzek , Charan Gurumurthy
发明人： Michael Walk , Hamid Azimi , John Guzek , Charan Gurumurthy
IPC分类号： H01L21/48 , H01L23/498 , H01L23/52 , H05K1/02 , H05K1/16
CPC分类号： H05K1/0271 , H01L23/49827 , H01L23/49833 , H01L2224/16 , H01L2924/01019 , H01L2924/15312 , H01L2924/15313 , H05K1/162 , H05K3/4688 , H05K2201/0133 , H05K2201/09481 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734
摘要： A system may include a coreless substrate, a layer of material attached to the substrate, the layer of material having a lower elastic modulus than the substrate, an interposer coupled to the layer of material, and a capacitive layer coupled to the interposer.
摘要翻译：系统可以包括无芯衬底，附着到衬底的材料层，具有比衬底更低的弹性模量的材料层，耦合到材料层的插入器以及耦合到插入器的电容层。

2. 发明申请

US20100044862A1 METHOD OF FORMING COLLAPSE CHIP CONNECTION BUMPS ON A SEMICONDUCTOR SUBSTRATE 有权
标题翻译：在半导体基板上形成接头片连接片的方法
公开(公告)号：US20100044862A1
公开(公告)日：2010-02-25
申请号：US12195339
申请日：2008-08-20
申请人： Ravi Nalla , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Ravi Nalla , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H05K3/243 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03828 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/11334 , H01L2224/13007 , H01L2224/13023 , H01L2224/13111 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/3025 , H05K3/28 , H05K3/4602 , H05K2201/0367 , H05K2203/041 , H05K2203/043 , H05K2203/054
摘要： A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
摘要翻译：提供一种在半导体衬底上形成崩溃芯片连接凸块的方法。该方法包括提供半导体衬底，该半导体衬底在半导体衬底的顶表面上具有多个凸块通孔，并且电镀多个凸点通孔以在半导体衬底的顶表面上形成多个通孔焊盘。该方法还包括在半导体衬底的顶表面上设置多个焊料微球，其中每个焊料微球放置在半导体衬底上的相应的通孔焊盘上并回流多个焊料微球以在其上形成塌陷芯片连接凸块半导体衬底。

3. 发明授权

US08440916B2 Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method 有权
标题翻译：使用微孔激光钻孔和导电层预图案形成基板芯结构的方法和根据该方法形成的基板芯结构
公开(公告)号：US08440916B2
公开(公告)日：2013-05-14
申请号：US11769900
申请日：2007-06-28
申请人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H05K1/11
CPC分类号： H05K1/115 , H05K1/0298 , H05K1/0306 , H05K1/18 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/426 , H05K3/427 , H05K3/429 , H05K3/4644 , H05K3/4652 , H05K2201/0394 , H05K2201/09563 , H05K2201/0959 , H05K2201/0969 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
摘要翻译：制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二补充图案化导电层提供到第一和第二辅助绝缘层的相应的一个上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层其中。

4. 发明授权

US07985622B2 Method of forming collapse chip connection bumps on a semiconductor substrate 有权
标题翻译：在半导体衬底上形成崩溃芯片连接凸块的方法
公开(公告)号：US07985622B2
公开(公告)日：2011-07-26
申请号：US12195339
申请日：2008-08-20
申请人： Ravi Nalla , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Ravi Nalla , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H01L21/44 , B23K31/00
CPC分类号： H05K3/243 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03828 , H01L2224/0401 , H01L2224/0558 , H01L2224/05644 , H01L2224/11334 , H01L2224/13007 , H01L2224/13023 , H01L2224/13111 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/3025 , H05K3/28 , H05K3/4602 , H05K2201/0367 , H05K2203/041 , H05K2203/043 , H05K2203/054
摘要： A method of forming collapse chip connection bumps on a semiconductor substrate is provided. The method includes providing a semiconductor substrate having a plurality of bump vias on a top surface of the semiconductor substrate and electroplating the plurality of bump vias to form a plurality of via pads on the top surface of the semiconductor substrate. The method also includes disposing a plurality of solder microballs on the top surface of the semiconductor substrate, wherein each solder microball is placed on a corresponding via pad on the semiconductor substrate and reflowing the plurality of solder microballs to form the collapse chip connection bumps on the semiconductor substrate.
摘要翻译：提供一种在半导体衬底上形成崩溃芯片连接凸块的方法。该方法包括提供半导体衬底，该半导体衬底在半导体衬底的顶表面上具有多个凸块通孔，并且电镀多个凸点通孔以在半导体衬底的顶表面上形成多个通孔焊盘。该方法还包括在半导体衬底的顶表面上设置多个焊料微球，其中每个焊料微球放置在半导体衬底上的相应的通孔焊盘上并回流多个焊料微球以在其上形成塌陷芯片连接凸块半导体衬底。

5. 发明申请

US20130242498A1 METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER DRILLING AND CONDUCTIVE LAYER PRE-PATTERNING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD 审中-公开
标题翻译：使用微晶激光钻孔和导电层预制图形成基底结构的方法和根据该方法形成的基体核心结构
公开(公告)号：US20130242498A1
公开(公告)日：2013-09-19
申请号：US13861338
申请日：2013-04-11
申请人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H05K1/02
CPC分类号： H05K1/115 , H05K1/0298 , H05K1/0306 , H05K1/18 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/426 , H05K3/427 , H05K3/429 , H05K3/4644 , H05K3/4652 , H05K2201/0394 , H05K2201/09563 , H05K2201/0959 , H05K2201/0969 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.
摘要翻译：制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二辅助图案化导电层提供到第一和第二辅助绝缘层的相应的第一和第二补充绝缘层上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层侧。

6. 发明授权

US09648733B2 Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning and substrate core structure formed according to the method 有权
公开(公告)号：US09648733B2
公开(公告)日：2017-05-09
申请号：US13861338
申请日：2013-04-11
申请人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H05K1/02 , H05K3/00 , H05K3/42 , H05K3/46
CPC分类号： H05K1/115 , H05K1/0298 , H05K1/0306 , H05K1/18 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/426 , H05K3/427 , H05K3/429 , H05K3/4644 , H05K3/4652 , H05K2201/0394 , H05K2201/09563 , H05K2201/0959 , H05K2201/0969 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof.

7. 发明申请

US20090002958A1 Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method 有权
标题翻译：使用微孔激光钻孔和导电层形成基板芯结构的方法根据该方法形成预图案和基板芯结构
公开(公告)号：US20090002958A1
公开(公告)日：2009-01-01
申请号：US11769900
申请日：2007-06-28
申请人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
发明人： Yonggang Li , Islam Salama , Charan Gurumurthy , Hamid Azimi
IPC分类号： H05K1/02 , H05K3/00
CPC分类号： H05K1/115 , H05K1/0298 , H05K1/0306 , H05K1/18 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/426 , H05K3/427 , H05K3/429 , H05K3/4644 , H05K3/4652 , H05K2201/0394 , H05K2201/09563 , H05K2201/0959 , H05K2201/0969 , Y10T29/49126 , Y10T29/49155 , Y10T29/49165
摘要： A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof.
摘要翻译：制造衬底芯结构的方法包括：在起始绝缘层的每一侧上提供限定开口的第一和第二图案化导电层; 在第一和第二图案化导电层的相应的一个上提供第一和第二辅助绝缘层; 激光钻孔延伸穿过第一和第二图案化导电层的至少一些导电层开口的一组通孔; 用导电材料填充该组通孔开口以提供一组导电通路; 以及将第一和第二补充图案化导电层提供到第一和第二辅助绝缘层的相应的一个上，该导电通孔的一侧接触第一补充图案化导电层，另一侧接触第二补充图案化导电层其中。

8. 发明申请

US20110254124A1 FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES 有权
标题翻译：形成功能化载体结构与无缝包装
公开(公告)号：US20110254124A1
公开(公告)日：2011-10-20
申请号：US12761782
申请日：2010-04-16
申请人： Ravi K. Nalla , John Guzek , Javier Soto Gonzalez , Drew Delaney , Hamid Azimi
发明人： Ravi K. Nalla , John Guzek , Javier Soto Gonzalez , Drew Delaney , Hamid Azimi
IPC分类号： H01L27/08 , H01L23/552 , B32B38/10
CPC分类号： H01L23/49822 , H01L21/02109 , H01L21/561 , H01L21/568 , H01L21/76897 , H01L23/4824 , H01L23/498 , H01L23/49866 , H01L23/5226 , H01L23/552 , H01L23/645 , H01L24/19 , H01L24/20 , H01L25/16 , H01L2221/68359 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/73267 , H01L2224/83005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/1206 , H01L2924/14 , H01L2924/1436 , H01L2924/18162 , H01L2924/3511 , H05K1/185 , H05K3/4682 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
摘要翻译：描述了形成微电子封装结构的方法及由此形成的相关结构。这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

9. 发明授权

US06600233B2 Integrated circuit package with surface mounted pins on an organic substrate 有权
公开(公告)号：US06600233B2
公开(公告)日：2003-07-29
申请号：US10142576
申请日：2002-05-08
申请人： Hwai-Peng Yeoh , Hamid Azimi , Amir Nur Rashid Wagiman , Mirng-Ji Lii
发明人： Hwai-Peng Yeoh , Hamid Azimi , Amir Nur Rashid Wagiman , Mirng-Ji Lii
IPC分类号： H01L2144
CPC分类号： H05K3/3463 , H01L21/4853 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/01087 , H01L2924/15153 , H01L2924/15165 , H01L2924/00 , H01L2224/0401
摘要： An integrated circuit package fabricated by attaching a surface mount pin to a pin pad on a substrate using a Sn—Sb solder composition, where the quantity of Sb is in a range from 4 percent to 10 percent by weight. The Sn—Sb composition has a melting point above the melting point of commonly-used Sn—Pb solders. Thus, after the pins are surface mounted to the substrate, the pin integrity is not later compromised by assembly steps that reheat the substrate to a temperature sufficient to reflow the Sn—Pb solder. In one embodiment, the surface mount pins are attached to the bottom surface of an organic substrate using the Sn—Sb composition, and a flip-chip is attached to the top surface using Sn—Pb solder bumps. An integrated circuit package includes the substrate, the surface mount pins, and the Sn—Sb solder composition on the bonding surfaces of the pins.

10. 发明授权

US07005727B2 Low cost programmable CPU package/substrate 失效
标题翻译：低成本可编程CPU封装/基板
公开(公告)号：US07005727B2
公开(公告)日：2006-02-28
申请号：US10234030
申请日：2002-09-03
申请人： Hamid Azimi , Debabrata Gupta , Saliya Witharana
发明人： Hamid Azimi , Debabrata Gupta , Saliya Witharana
IPC分类号： H01L23/58
CPC分类号： H01L21/485 , H01L23/5382 , H01L2924/0002 , Y10S257/91 , H01L2924/00
摘要： A programmable package with a fuse embedded therein, and fabrication method are provided. The fuse has first and second terminal ends joined by a central portion defining a fusible link. The ends include a portion of the first and second conductive layers, the central portion including a portion of the first conductive layer. The first layer may be electroless copper and the second layer may be electrolytic copper. The fuse may have a dog-bone or a bow tie shape. The method includes providing a substrate with a dielectric layer, and forming the fuse by depositing first conductive layer, forming and patterning second conductive layer over a portion of the first layer, and patterning first layer to form interconnects between areas of the second layer.
摘要翻译：提供了嵌入其中的熔丝的可编程封装以及制造方法。保险丝具有由限定可熔连接件的中心部分连接的第一和第二端部。端部包括第一和第二导电层的一部分，中心部分包括第一导电层的一部分。第一层可以是无电解铜，第二层可以是电解铜。保险丝可能具有狗骨或蝴蝶结的形状。该方法包括：提供具有电介质层的衬底，以及通过沉积第一导电层形成熔丝，在第一层的一部分上形成和图案化第二导电层，以及图案化第一层以在第二层的区域之间形成互连。

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