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1. 发明授权

US07451931B2 Detecting barcodes on two-dimensional images using frequency domain data 有权
标题翻译：使用频域数据检测二维图像上的条形码
公开(公告)号：US07451931B2
公开(公告)日：2008-11-18
申请号：US11389691
申请日：2006-03-27
申请人： Michael W. Dant , Robert A. Kohtz
发明人： Michael W. Dant , Robert A. Kohtz
IPC分类号： G06K7/10
CPC分类号： G06K7/1443 , G06K7/10712 , G06K7/1456
摘要： A system and method of detecting a barcode involves obtaining a two-dimensional source image and converting it into a frequency domain image (FDI). Frequency trends in the FDI are then analyzed to determine whether barcode information is present in the FDI. In this way, the presence, location, orientation, size and symbology of a barcode can be quickly and accurately determined.
摘要翻译：检测条形码的系统和方法包括获得二维源图像并将其转换成频域图像（FDI）。然后分析FDI的频率趋势，以确定条形码信息是否存在于FDI中。以这种方式，可以快速准确地确定条形码的存在，位置，方向，大小和符号。

2. 发明授权

US5872967A Method for warm boot from reset 失效
标题翻译：从复位启动的方法
公开(公告)号：US5872967A
公开(公告)日：1999-02-16
申请号：US607445
申请日：1996-02-27
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F1/00 , G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F12/06 , G06F12/14 , G06F21/00
CPC分类号： G06F9/5016 , G06F12/0638 , G06F21/79 , G06F9/30101 , G06F9/32 , G06F9/4401 , G06F12/1433 , G06F2211/1097
摘要： A computer system employs a process on warm boot which obviates the need to copy code in non-volatile memory to volatile memory; a normal function in a warm boot process. The computer system checks a warm boot flag which indicates that the code was previously copied on cold boot. By avoiding copying this already copied code and executing directly from the volatile memory considerable time is saved. Since BIOS code is typically on the order of 10K bytes, elimination of the necessity to rewrite BIOS and vectoring directly to BIOS image file in RAM saves on the order of ten thousand clock cycles.
摘要翻译：计算机系统采用热启动的过程，其消除了将非易失性存储器中的代码复制到易失性存储器的需要; 在热启动过程中的正常功能。计算机系统检查一个热启动标志，指示该代码以前是在冷启动时复制的。通过避免复制已经复制的代码并直接从易失性存储器执行，可以节省大量时间。由于BIOS代码通常在10K字节的数量级上，所以不需要重新编写BIOS并直接向导到RAM中的BIOS映像文件就可以节省一万个时钟周期。

3. 发明授权

US5822601A Apparatus to allow a CPU to control the relocation of code blocks for other CPUs 失效
标题翻译：允许CPU控制其他CPU的代码块重定位的装置
公开(公告)号：US5822601A
公开(公告)日：1998-10-13
申请号：US549304
申请日：1995-10-27
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F12/06 , G06F21/00 , G06F9/355
CPC分类号： G06F9/30141 , G06F12/0623 , G06F15/177 , G06F21/79 , G06F9/30101 , G06F9/32 , G06F9/4405 , G06F9/5016
摘要： The invention provides for a CPU in a digital system to control the location of the code being executed by one or more peripheral CPUs when all CPUs share a common memory. This allows the CPU to allocate convenient (e.g., unused) blocks of its address space for the code for the peripheral CPU(s). Additionally, for digital systems in which the peripheral CPU(s) cannot address the full range of the address space of the shared memory that is available to the CPU, the CPU can control the relocation of the block of code for the peripheral CPU(s) (i.e., provide a code paging system).
摘要翻译：本发明提供了一种数字系统中的CPU来控制当所有CPU共享共同存储器时由一个或多个外围CPU执行的代码的位置。这允许CPU为外围CPU的代码分配其地址空间的方便（例如，未使用的）块。另外，对于其中外围CPU不能解决CPU可用的共享存储器的地址空间的全部范围的数字系统，CPU可以控制外围CPU的代码块的重新定位）（即提供代码分页系统）。

4. 发明授权

US5752063A Write inhibited registers 失效
标题翻译：写禁止寄存器
公开(公告)号：US5752063A
公开(公告)日：1998-05-12
申请号：US575004
申请日：1995-12-19
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F11/00 , G06F21/00 , G06F12/00
CPC分类号： G06F9/5016 , G06F11/006 , G06F21/79 , G06F9/30101 , G06F9/30141 , G06F9/32 , G06F9/4401
摘要： The invention provides a simple I/O port which can be used to support a variety of system functions such as a revision, configuration or identification register. This port is provided with a means to be programmable once, upon system power-up so that changes to the port contents are possible, but only under controlled conditions. Once the register has been programmed, it will no longer respond to writes.
摘要翻译：本发明提供了一种简单的I / O端口，可用于支持各种系统功能，如修订版，配置或标识寄存器。该端口具有一次可编程的方式，在系统上电时，可以对端口内容进行更改，但只能在受控条件下进行。一旦寄存器被编程，它将不再响应写入。

5. 发明授权

US06161162A Multiprocessor system for enabling shared access to a memory 失效
标题翻译：用于启用对存储器的共享访问的多处理器系统
公开(公告)号：US06161162A
公开(公告)日：2000-12-12
申请号：US480047
申请日：1995-06-06
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Richard D. Ball , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz , Jimmy D. Smith
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Richard D. Ball , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz , Jimmy D. Smith
IPC分类号： G06F1/00 , G06F9/30 , G06F9/445 , G06F12/14 , G06F21/00 , G06F13/18
CPC分类号： G06F21/79 , G06F9/30101 , G06F9/4401 , G06F12/1433 , G06F2211/1097
摘要： A multiprocessing computer system and method providing multiplexed address and data paths from multiple CPUs to a single storage device. These paths are controlled by an arbitration circuit which allows one CPU to always have the highest priority. The primary CPU may or may not be the highest priority CPU in the arbitration scheme. The arbitration circuit is combined with a controlling mechanism which interfaces to the memory device. This controller operates at a clock rate fast enough to allow the highest priority CPU to access the memory at it's highest data rate and, yet, guarantees a maximum idle period for the lower priority CPU to wait for it's interleaved memory access to complete. A single memory device provides cost and space savings. A controller is responsive to these processors to multiplex their information signals for selectively conveying information present at their address and data ports. A common memory device is addressable by the processors, and responsive to the controller to share addressing of the common memory device.
摘要翻译：一种多处理计算机系统和方法，其将多个地址和数据路径从多个CPU提供给单个存储设备。这些路径由仲裁电路控制，仲裁电路允许一个CPU始终具有最高优先级。主CPU可能是也可能不是仲裁方案中最高优先级的CPU。仲裁电路与与存储器件接口的控制机构组合。该控制器的时钟速率足够快，允许最高优先级的CPU以最高数据速率访问存储器，而且保证较低优先级CPU等待其交错存储器访问完成的最大空闲时间。单个存储器件节省了成本和空间。控制器响应于这些处理器来复用其信息信号，以选择性地传送存在于其地址和数据端口的信息。公共存储器件可由处理器寻址，并响应于控制器共享公用存储器件的寻址。

6. 发明授权

US6009495A Protected address range in an electrically erasable programmable read only memory 失效
标题翻译：电可擦除可编程只读存储器中的保护地址范围
公开(公告)号：US6009495A
公开(公告)日：1999-12-28
申请号：US554667
申请日：1995-11-08
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F12/14 , G06F21/00 , G06F12/00
CPC分类号： G06F9/5016 , G06F12/1433 , G06F21/79 , G06F9/30101 , G06F9/32 , G06F9/4401 , G06F12/1441
摘要： An interface between the host CPU and the programmably memory, providing an address, data and read/write control signals to create a non-volatile sector within the programmable memory. In an embodiment when the system reset is de-asserted immediately after power-on, the size of the protected EEPROM area is sensed on special strapping option pins and automatically configures the non-volatile sector. This allows the size of the protected area to be changed on the manufacturing line as needed for different applications. Once configured to protect a specific size and location in the non-volatile memory, the invention prevents the write control signal to the memory to be asserted when the address of the data access requested by the CPU is in the protected area of the memory. This has the effect of preventing modification of the protected area by a sector modification algorithm.
摘要翻译：主机CPU和可编程存储器之间的接口，提供地址，数据和读/写控制信号，以在可编程存储器内创建非易失性扇区。在系统复位在上电之后立即被断开的实施例中，受保护的EEPROM区域的大小在特殊的捆扎选项引脚上被感测并自动配置非易失性扇区。这样就可以根据不同的应用需要在生产线上改变保护区的大小。一旦配置为保护非易失性存储器中的特定尺寸和位置，本发明防止当CPU请求的数据访问的地址处于存储器的保护区域时，对存储器的写入控制信号被断言。这具有通过扇区修改算法防止保护区域的修改的效果。

7. 发明授权

US5867655A Method to store privileged data within the primary CPU memory space 失效
标题翻译：在主CPU内存空间内存储特权数据的方法
公开(公告)号：US5867655A
公开(公告)日：1999-02-02
申请号：US914733
申请日：1997-08-19
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Michael P. Krau , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F12/14 , G06F21/00 , G06F13/00
CPC分类号： G06F9/5016 , G06F21/79 , G06F9/30101 , G06F9/32 , G06F9/4401 , G06F12/1433
摘要： In the present invention, a single EEPROM is used to store firmware for the CPU, firmware for the SCP and the system password and other critical system data. Hardware protection is provided that prevents the CPU from accessing the portion of the EEPROM that contains the password or other critical systems data.
摘要翻译：在本发明中，单个EEPROM用于存储CPU的固件，SCP的固件和系统密码以及其他关键系统数据。提供硬件保护，防止CPU访问包含密码或其他关键系统数据的EEPROM部分。

8. 发明申请

US20090128509A1 EXTERNALLY RECONFIGURABLE INPUT SYSTEM 审中-公开
标题翻译：外部可重新输入系统
公开(公告)号：US20090128509A1
公开(公告)日：2009-05-21
申请号：US12266661
申请日：2008-11-07
申请人： Robert A. Kohtz , Stephen J. Kelly , Kraig D. Brody
发明人： Robert A. Kohtz , Stephen J. Kelly , Kraig D. Brody
IPC分类号： G06F3/041 , H03M11/04
CPC分类号： G06F1/1626 , G06F3/0202 , G06F3/041 , H01H2223/024 , H01H2223/028
摘要： An externally reconfigurable input system for an electronic device is provided. The input system has the flexibility of receiving input via an input interface with the guidance of key-based substrate overlay positioned proximate a sensor array that is coupled to a printed wiring assembly. An input correlation component receives signals generated by the sensor array in response to displacement of one or more keys associated with the key-based substrate. The key-based substrate overlay is removable so as to be reconfigured.
摘要翻译：提供了一种用于电子设备的外部可重新配置的输入系统。输入系统具有通过输入接口接收输入的灵活性，其中引导基于键的基板覆盖层位于靠近印刷线路组件的传感器阵列附近。输入相关分量响应于与基于键的衬底相关联的一个或多个键的位移，接收由传感器阵列产生的信号。基于键的衬底覆盖是可移动的，以便被重新配置。

9. 发明授权

US07392951B2 Methods, apparatuses and articles for automatic data collection devices, for example barcode readers, in cluttered environments 有权
标题翻译：用于自动数据采集设备（例如条形码读取器）在杂乱环境中的方法，设备和物品
公开(公告)号：US07392951B2
公开(公告)日：2008-07-01
申请号：US11436123
申请日：2006-05-16
申请人： Jim T. Ray , Robert A. Kohtz , Michael Dant , Jeffrey M. Hunt
发明人： Jim T. Ray , Robert A. Kohtz , Michael Dant , Jeffrey M. Hunt
IPC分类号： G06K7/10
CPC分类号： G06K7/10851
摘要： A reader such as a barcode reader identifies at least one potential target such as a barcode symbol in its field-of-view, and projects or transmits an indicator toward or proximate the potential target containing information about the respective potential target. Such information may include which target is currently active, the symbology in which the target is encoded, the relative position of the reader with respect to the target, the ability of the reader to decode the target, and/or ranked or sorted order information regarding the target and neighboring targets. The reader may rank, sort, prioritize or otherwise determine order based on various parameters, including symbology, position in field-of-view, size, etc., and may base such on past history of the reader and/or user, and may weight such.
摘要翻译：诸如条形码读取器的读取器识别至少一个潜在目标，例如其视野中的条形码符号，并且向包含关于各个潜在目标的信息的潜在目标投射或发送指示器。这样的信息可以包括当前活动的目标，目标被编码的符号系统，读者相对于目标的相对位置，读者解码目标的能力和/或关于目标和邻近目标。读者可以基于各种参数（包括符号系统，视野中的位置，大小等）对秩序进行排序，分类，排序或以其他方式确定顺序，并且可以将这些依赖于读取器和/或用户的过去历史，并且可以体重这样。

10. 发明授权

US5596713A Method to prevent data loss in an electrically erasable read only memory 失效
标题翻译：防止电可擦除只读存储器中的数据丢失的方法
公开(公告)号：US5596713A
公开(公告)日：1997-01-21
申请号：US478363
申请日：1995-06-07
申请人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
发明人： David T. DeRoo , Mark D. Nicol , David J. DeLisle , Saifuddin Fakhruddin , Lloyd W. Gauthier , Robert A. Kohtz
IPC分类号： G06F1/00 , G06F9/30 , G06F9/32 , G06F9/445 , G06F9/50 , G06F11/00 , G06F12/14 , G06F21/00 , G11C29/00
CPC分类号： G06F9/4401 , G06F11/004 , G06F12/1433 , G06F21/79 , G06F9/30101 , G06F9/30141 , G06F9/32 , G06F9/5016 , G11C29/88
摘要： An apparatus and method for tracking and interception of instructions as they are presented to the memory, selectively passing harmless data to the device and disallowing the sequences which instruct the device to perform harmful functions, such as self-erase. A software trap is provided to be transparent to the operation of the device and the host system, imposing no harmful timing delays or software overhead. Accordingly, the invention allows the use of standard electrically erasable read-only memories in an application which requires that the device be protected from global erasure. A hardware front end intercepts the software command which is used to globally erase the device. The apparatus receives address signals from the computer system corresponding to the protected peripheral device, receives data signals from the computer system to the protected peripheral device, tracks a predetermined sequence of address and address signals, substitutes at least one of the data signals received with a replacement data signal, and sends a replacement data signal.
摘要翻译：一种用于在将指令呈现给存储器时跟踪和截取指令的设备和方法，选择性地将无害数据传送到设备，并且禁止指示设备执行有害功能（例如自擦除）的序列。提供软件陷阱对设备和主机系统的操作是透明的，不会产生有害的定时延迟或软件开销。因此，本发明允许在需要保护设备免受全局擦除的应用中使用标准的电可擦除只读存储器。硬件前端拦截用于全局擦除设备的软件命令。该装置从对应于受保护的外围设备的计算机系统接收地址信号，从计算机系统接收数据信号到受保护的外围设备，跟踪预定的地址和地址信号序列，代替接收到的数据信号中的至少一个替换数据信号，并发送替换数据信号。

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