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    • 3. 发明申请
    • Analog storage cell with low leakage
    • 具有低泄漏的模拟存储单元
    • US20060087362A1
    • 2006-04-27
    • US11256632
    • 2005-10-21
    • Micah O'HalloranRahul Sarpeshkar
    • Micah O'HalloranRahul Sarpeshkar
    • H03K17/687
    • G11C27/024G11C27/02H03K17/162
    • An analog storage cell circuit includes a switch that minimizes subthreshold conduction and diode leakage, as well as an accumulation-mode coupling mechanism to minimize overall switch leakage to minimize accumulation-mode leakage. In one embodiment, an analog storage circuit includes a sample and hold circuit including an amplifier having first and second inputs and a switch coupled to the first input of the amplifier. The switch includes a first switching device forming a core of the switch, a second switching device coupled to the first switching device to disconnect the first switching device from a first terminal during the hold phase, and a third switching device coupled to the first switching device to connect the first switching device to a second terminal during the hold phase to minimize accumulation mode conduction in the first switching device.
    • 模拟存储单元电路包括使亚阈值导通和二极管泄漏最小化的开关,以及累积模式耦合机制,以最小化整体开关泄漏以最小化累积模式泄漏。 在一个实施例中,模拟存储电路包括采样和保持电路,其包括具有第一和第二输入的放大器和耦合到放大器的第一输入的开关。 开关包括形成开关的核心的第一开关装置,耦合到第一开关装置的第二开关装置,以在保持阶段期间将第一开关装置与第一端子断开;以及第三开关装置,其耦合到第一开关装置 以在保持阶段期间将第一开关器件连接到第二端子,以最小化第一开关器件中的累积模式导通。