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1. 发明授权

US08723314B2 Semiconductor workpiece with backside metallization and methods of dicing the same 有权
标题翻译：具有背面金属化的半导体工件及其切割方法
公开(公告)号：US08723314B2
公开(公告)日：2014-05-13
申请号：US13408102
申请日：2012-02-29
申请人： Michael Su , Lei Fu , Edward S. Alcid
发明人： Michael Su , Lei Fu , Edward S. Alcid
IPC分类号： H01L23/498 , H01L21/30
CPC分类号： H01L21/78
摘要： Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.
摘要翻译：公开了各种半导体工件及其切割方法。一方面，提供一种制造方法，其包括在半导体工件的背面上的金属化结构中形成通道。半导体工件包括基板。该通道与半导体芯片正面上的切割街大致对准。

2. 发明申请

US20130221517A1 SEMICONDUCTOR WORKPIECE WITH BACKSIDE METALLIZATION AND METHODS OF DICING THE SAME 有权
标题翻译：具有背面金属化的半导体工件及其制造方法
公开(公告)号：US20130221517A1
公开(公告)日：2013-08-29
申请号：US13408102
申请日：2012-02-29
申请人： Michael Su , Lei Fu , Edward S. Alcid
发明人： Michael Su , Lei Fu , Edward S. Alcid
IPC分类号： H01L23/498 , H01L21/50
CPC分类号： H01L21/78
摘要： Various semiconductor workpieces and methods of dicing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a channel in a metallization structure on a backside of a semiconductor workpiece. The semiconductor workpiece includes a substrate. The channel is in substantial alignment with a dicing street on a front side of the semiconductor chip.
摘要翻译：公开了各种半导体工件及其切割方法。一方面，提供一种制造方法，其包括在半导体工件的背面上的金属化结构中形成通道。半导体工件包括基板。该通道与半导体芯片正面上的切割街大致对准。

3. 发明授权

US06632690B2 Method of fabricating reliable laminate flip-chip assembly 有权
标题翻译：制造可靠的层压倒装芯片组装方法
公开(公告)号：US06632690B2
公开(公告)日：2003-10-14
申请号：US10062407
申请日：2002-02-05
申请人： Raj N. Master , Edward S. Alcid , Diong-Hing Ding
发明人： Raj N. Master , Edward S. Alcid , Diong-Hing Ding
IPC分类号： G01R3126
CPC分类号： H05K3/3478
摘要： A method of fabricating laminate assemblies determines the ideal weight (W) of underfill to be dispensed, based on the size of the semiconductor die and the gap between the die and the laminate substrate. Underfill is dispensed in a single step in an amount between 1.1W and 1.3W to form fillets that cover at least 15% of the height of the semiconductor die on all four sides of the die. The amount of underfill ensures that the fillet coverage imbalance is 30% or less for each of the pairs of opposing sides of the die, thereby improving solder joint reliability.
摘要翻译：基于半导体管芯的尺寸和管芯与层叠基板之间的间隙，制造叠层组件的方法决定了要分配的底部填充物的理想重量（W）。底部填充剂以1.1W至1.3W之间的一个步骤进行分配，以形成在模具的四面上覆盖半导体管芯高度的至少15％的圆角。底部填充剂的数量确保了模具的每对相对侧的圆角覆盖不平衡为30％以下，从而提高焊点的可靠性。

4. 发明申请

US20130105975A1 SEMICONDUCTOR CHIP DEVICE WITH THERMAL INTERFACE MATERIAL FRAME 审中-公开
标题翻译：具有热界面材料框架的半导体芯片器件
公开(公告)号：US20130105975A1
公开(公告)日：2013-05-02
申请号：US13282310
申请日：2011-10-26
申请人： Rafiqul Hussain , Edward S. Alcid
发明人： Rafiqul Hussain , Edward S. Alcid
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L23/24 , H01L21/563 , H01L23/36 , H01L23/498 , H01L23/50 , H01L24/13 , H01L24/16 , H01L24/26 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/97 , H01L25/0657 , H01L2224/131 , H01L2224/16145 , H01L2224/16225 , H01L2224/26145 , H01L2224/26175 , H01L2224/27013 , H01L2224/29109 , H01L2224/29124 , H01L2224/29144 , H01L2224/29147 , H01L2224/29155 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/33505 , H01L2224/33517 , H01L2224/33519 , H01L2224/73204 , H01L2224/73253 , H01L2224/81815 , H01L2224/83002 , H01L2224/83102 , H01L2224/83104 , H01L2224/92125 , H01L2224/97 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2924/10252 , H01L2924/10253 , H01L2924/14 , H01L2924/1431 , H01L2924/1531 , H01L2924/157 , H01L2924/19105 , H01L2924/014 , H01L2224/81 , H01L2924/00
摘要： Various semiconductor chip devices and methods of assembling the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a frame to a surface of a substrate. The surface of the substrate is adapted to hold a first semiconductor chip that includes an upper surface. The frame includes an internal wall that is adapted to engage plural sidewalls of the first semiconductor chip. A portion of the internal wall and at least a portion of the upper surface are adapted to define an internal space.
摘要翻译：公开了各种半导体芯片器件及其组装方法。在一个方面，提供了一种制造方法，其包括将框架耦合到基板的表面。衬底的表面适于保持包括上表面的第一半导体芯片。框架包括适于接合第一半导体芯片的多个侧壁的内壁。内壁的一部分和上表面的至少一部分适于限定内部空间。

5. 发明授权

US06483169B1 Extruded heat spreader 有权
标题翻译：挤压散热器
公开(公告)号：US06483169B1
公开(公告)日：2002-11-19
申请号：US09892777
申请日：2001-06-28
申请人： Eric S. Tosaya , Edward S. Alcid
发明人： Eric S. Tosaya , Edward S. Alcid
IPC分类号： H01L3111
CPC分类号： H01L23/367 , H01L2224/73253
摘要： An extruded heat exchanger that reduces manufacturing costs and material waste, without compromising heat spreading effects. The heat exchanger has an upper surface that is thermally coupled to a heat sink. Two sidewalls extend only from opposite edges of the upper surface. A flange extends from each of the opposing sidewalls.
摘要翻译：一种挤压式热交换器，可以降低制造成本和材料浪费，而不会影响散热效果。热交换器具有热耦合到散热器的上表面。两个侧壁仅从上表面的相对边缘延伸。凸缘从每个相对的侧壁延伸。

6. 发明授权

US06538320B1 Heat spreader having holes for rivet-like adhesive connections 有权
标题翻译：具有铆钉状粘合剂连接孔的散热器
公开(公告)号：US06538320B1
公开(公告)日：2003-03-25
申请号：US09892778
申请日：2001-06-28
申请人： Eric S. Tosaya , Edward S. Alcid
发明人： Eric S. Tosaya , Edward S. Alcid
IPC分类号： H01L2310
CPC分类号： H01L21/50 , H01L23/36 , H01L2924/0002 , H01L2924/00
摘要： A heat spreader-package assembly is provided having a heat spreader mounted to a package board with an adhesive. The heat spreader has an upper portion and a plurality of sidewalls extending from the upper portion. The heat spreader has a flange that extends from the sidewalls continuously about a periphery of the upper portion and has a plurality of holes. The holes allow the uncured adhesive to flow therethrough. When the adhesive has cured, a head is formed from the adhesive on an upper side of the flange to establish a riveted connection.
摘要翻译：提供了一种散热器 - 包装组件，其具有用粘合剂安装到封装板的散热器。散热器具有从上部延伸的上部和多个侧壁。散热器具有从侧壁连续地围绕上部周边延伸的凸缘，并且具有多个孔。这些孔允许未固化的粘合剂流过其中。当粘合剂固化时，在法兰的上侧上由粘合剂形成头，以形成铆接连接。

7. 发明授权

US06442234B1 X-ray inspection of ball contacts and internal vias 失效
标题翻译：球形触点和内部通孔的X射线检查
公开(公告)号：US06442234B1
公开(公告)日：2002-08-27
申请号：US09677845
申请日：2000-10-03
申请人： David B. Morken , Edward S. Alcid
发明人： David B. Morken , Edward S. Alcid
IPC分类号： G01N2302
CPC分类号： G01N23/04
摘要： A method for performing inspection of raised electrical contacts, such as BGA and flip-chip-type contacts, and associated underlying vias. An electrical or electronic device or component having a major surface is provided including an array of closely spaced apart BGA flip-chip-type raised contacts with respective underlying vias. An area-of-interest (AOI), including at least one BGA or flip-chip-type contact/via structure is selected. The row containing the AOI is isolated, by computed tomography imaging, via electrical testing, or by removal, for example, from the electrical or electronic device or component. The AOI is mounted on an X-ray transparent substrate; and X-ray transmission imaging of the AOI is performed to inspect the at least one BGA or flip-chip-type contact/via structure for the presence of misalignments, voids, and delaminations.
摘要翻译：用于执行诸如BGA和倒装芯片型触点之类的升高的电触点的检查方法以及相关的底部通孔。提供具有主表面的电气或电子设备或部件，其包括具有相应底部通孔的紧密间隔开的BGA倒装芯片型凸起触头的阵列。选择感兴趣区域（AOI），包括至少一个BGA或倒装片型接触/通孔结构。包含AOI的行通过计算机断层扫描成像，通过电气测试或通过例如从电气或电子设备或部件移除来隔离。 AOI安装在X射线透明基板上; 并且进行AOI的X射线透射成像以检查至少一个BGA或倒装芯片型接触/通孔结构以存在不对准，空隙和分层的存在。

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