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1. 发明申请

US20070061555A1 Call return tracking technique 审中-公开
标题翻译：呼叫返回跟踪技术
公开(公告)号：US20070061555A1
公开(公告)日：2007-03-15
申请号：US11229177
申请日：2005-09-15
申请人： Michael St. Clair , Boyd Phelps , Stephan Jourdan
发明人： Michael St. Clair , Boyd Phelps , Stephan Jourdan
IPC分类号： G06F9/44
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3861 , G06F9/4486
摘要： Method, apparatus, and system for tracking call returns. At least one embodiment maps the locations of a return instruction pointer within a speculative return stack buffer and a committed return stack buffer to determine a return stack buffers from which the return instruction pointer should be retrieved.
摘要翻译：用于跟踪呼叫回报的方法，设备和系统。至少一个实施例将返回指令指针的位置映射在推测返回堆栈缓冲器和承诺返回堆栈缓冲器中，以确定返回堆栈缓冲区，从该缓冲区中应该检索返回指令指针。

2. 发明申请

US20050135178A1 Memory array with staged output 失效
标题翻译：具有分段输出的内存阵列
公开(公告)号：US20050135178A1
公开(公告)日：2005-06-23
申请号：US10739268
申请日：2003-12-19
申请人： Stephan Jourdan , Boyd Phelps , Chris Yuker
发明人： Stephan Jourdan , Boyd Phelps , Chris Yuker
IPC分类号： G11C7/10 , G11C8/00 , G11C11/413
CPC分类号： G11C7/1075 , G11C11/413
摘要： Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.
摘要翻译：本发明的实施例提供了一种用于将从可寻址存储器位置输出的数据分段为多个场的方法和系统。在实施例中，可以在不同的时钟周期期间输出存储在地址处的数据项的每个字段。在另外的实施例中，可以首先输出大多数时间关键字段。

3. 发明申请

US20050132174A1 Predicting instruction branches with independent checking predictions 审中-公开
标题翻译：用独立检查预测预测指令分支
公开(公告)号：US20050132174A1
公开(公告)日：2005-06-16
申请号：US10735675
申请日：2003-12-16
申请人： Stephan Jourdan , Boyd Phelps , Mark Davis
发明人： Stephan Jourdan , Boyd Phelps , Mark Davis
IPC分类号： G06F9/00 , G06F9/38
CPC分类号： G06F9/3806 , G06F9/3848 , G06F9/3851
摘要： Systems and methods of predicting instruction branches provide for independent checking predictions and dynamic next-line predictions. Next-line predictions may also have a latency that is a plurality of clock cycles, where the next line predictions include group predictions. Each group prediction includes a plurality of target addresses corresponding to their plurality of clock cycles. The plurality of target addresses can include a leaf target and one or more intermediate targets, where the leaf target defines a target address of the group prediction.
摘要翻译：预测指令分支的系统和方法提供独立的检查预测和动态下一行预测。下一行预测还可能具有多个时钟周期的延迟，其中下一行预测包括组预测。每个组预测包括对应于它们的多个时钟周期的多个目标地址。多个目标地址可以包括叶目标和一个或多个中间目标，其中叶目标定义组预测的目标地址。

4. 发明申请

US20060098518A1 Memory array with staged output 有权
公开(公告)号：US20060098518A1
公开(公告)日：2006-05-11
申请号：US11315160
申请日：2005-12-23
申请人： Stephan Jourdan , Boyd Phelps , Chris Yuker
发明人： Stephan Jourdan , Boyd Phelps , Chris Yuker
IPC分类号： G11C8/00
CPC分类号： G11C7/1075 , G11C11/413
摘要： Embodiments of the present invention provide a method and system for staging the data output from an addressable memory location as a plurality of fields. In embodiments, each field of a data item that is stored at an address may be output during a different clock cycle. In further embodiments, the most time critical field may be output first.

5. 发明授权

US09146745B2 Method and apparatus for partitioned pipelined execution of multiple execution threads 有权
标题翻译：分割流水线执行多个执行线程的方法和装置
公开(公告)号：US09146745B2
公开(公告)日：2015-09-29
申请号：US11479245
申请日：2006-06-29
申请人： Stephan Jourdan , Robert Hinton
发明人： Stephan Jourdan , Robert Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3804 , G06F9/3844
摘要： Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.
摘要翻译：用于分割微处理器流水线以支持流水线分支预测和多个执行线程的指令获取的方法和装置。线程选择阶段从多个执行线程中选择线程。在一个实施例中，分支预测输出队列中的存储被预分配给一个分支预测阶段中的线程的一部分，以便防止分支预测流水线中后续阶段的停顿。在另一个实施例中，指令提取阶段在与所选线程的一部分相对应的获取地址处获取指令。如果有足够的存储可用，另一个指令获取阶段将指令数据存储在指令提取输出队列中。否则，与所选线程相对应的指令获取阶段无效并被重新设计，以避免在指令提取流水线中停止前进阶段，这可能是获取另一线程的指令。

6. 发明授权

US09021279B2 Independent power control of processing cores 有权
公开(公告)号：US09021279B2
公开(公告)日：2015-04-28
申请号：US13087073
申请日：2011-04-14
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

7. 发明授权

US08510536B2 Vector completion mask handling 有权
标题翻译：矢量完成掩码处理
公开(公告)号：US08510536B2
公开(公告)日：2013-08-13
申请号：US13535685
申请日：2012-06-28
申请人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
发明人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
IPC分类号： G06F15/00 , G06F15/76
CPC分类号： G06F9/3824 , G06F9/30036 , G06F15/8084
摘要： Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.
摘要翻译：提供矢量完成掩码（VCM）处理技术。数据结构包括用于特定操作的每个操作数的掩码字段。处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

8. 发明申请

US20120272046A1 Vector Completion Mask Handling 有权
标题翻译：矢量完成面具处理
公开(公告)号：US20120272046A1
公开(公告)日：2012-10-25
申请号：US13535685
申请日：2012-06-28
申请人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
发明人： Stephan Jourdan , Michael Fetterman , Michael Cornaby , Per Hammarlund , Ronak Signhal , Glenn Hinton
IPC分类号： G06F9/302
CPC分类号： G06F9/3824 , G06F9/30036 , G06F15/8084
摘要： Techniques for vector completion mask (VCM) handling are provided. A data structure includes a mask field for each operand of a particular operation. A processor attempts to execute the operation with multiple operands, which are identified in the data structure by the mask fields. If operands are successfully retrieved for execution with the operation, then the corresponding mask field within the data structure is cleared. The processor can reset if any field remains set within the data structure and can re-process the operation with operands that were not previously handled with the operation.
摘要翻译：提供矢量完成掩码（VCM）处理技术。数据结构包括用于特定操作的每个操作数的掩码字段。处理器尝试通过掩码字段在数据结构中标识的多个操作数来执行操作。如果成功检索操作数以执行操作，则数据结构中的相应掩码字段将被清除。如果任何字段在数据结构中保持设置，并且可以使用以前未被操作的操作数重新处理操作，则处理器可以重置。

9. 发明授权

US08103831B2 Efficient method and apparatus for employing a micro-op cache in a processor 有权
标题翻译：在处理器中采用微操作高速缓存的高效方法和装置
公开(公告)号：US08103831B2
公开(公告)日：2012-01-24
申请号：US12060239
申请日：2008-03-31
申请人： Lihu Rappoport , Bob Valentine , Stephan Jourdan , Yoav Almog , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
发明人： Lihu Rappoport , Bob Valentine , Stephan Jourdan , Yoav Almog , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
IPC分类号： G06F12/00
CPC分类号： G06F9/3017 , G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/30145 , G06F9/3802 , G06F9/382 , Y02D10/171
摘要： Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.
摘要翻译：公开了在处理器中使用微操作高速缓存的方法和装置。指令指针的标签匹配检索一组具有匹配标签的微操作高速缓存行访问元组。该集合存储在匹配队列中。来自匹配队列的线路访问元组用于访问微操作高速缓存数据阵列中的高速缓存行以提供微操作队列。在微操作缓存未命中时，宏指令转换引擎（MITE）解码宏指令以提供微操作队列。指令指针存储在从MITE获取宏指令的小队列中。当缺席队列为空时，MITE可能会被禁用以节省电力，而当匹配队列为空时，也可以为微操作高速缓存数据阵列。随后微操作高速缓存未命中的微操作高速缓存中的最后一个微操作中的同步标志指示来自MITE的微操作与微操作高速缓存的微操作合并。

10. 发明授权

US08069358B2 Independent power control of processing cores 有权
标题翻译：处理核心的独立功率控制
公开(公告)号：US08069358B2
公开(公告)日：2011-11-29
申请号：US12545657
申请日：2009-08-21
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译：两个或多个处理核心的独立功率控制。更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。

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