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1. 发明申请

US20200066105A9 SYSTEMS AND METHODS FOR ENABLING REMOTE DEVICE USERS TO WAGER ON MICRO EVENTS OF GAMES IN A DATA NETWORK ACCESSIBLE GAMING ENVIRONMENT 审中-公开
公开(公告)号：US20200066105A9
公开(公告)日：2020-02-27
申请号：US15978577
申请日：2018-05-14
申请人： Michael Shore , Alfonso Chan , Luis Ortiz , Kermit Lopez
发明人： Michael Shore , Alfonso Chan , Luis Ortiz , Kermit Lopez
IPC分类号： G07F17/32 , G06Q20/32
摘要： A method and system for micro-betting. One or more micro-bets can be electronically placed with respect to one or more micro-events associated with an event during a round of micro-betting. One or more wages with respect to the micro-bet(s) can be managed and controlled during the round of micro-betting. The wager(s) can be managed and controlled remote from electronically placing the micro-bet(s) during the round of micro-betting. Additionally, a portion of a profit can be automatically obtained with respect to the round of micro-bets in exchange for the aforementioned managing and controlling of the wager(s) with respect to the micro-bet(s) during the round of micro-betting.

2. 发明申请

US20080036652A1 Positioning system and method 有权
标题翻译：定位系统及方法
公开(公告)号：US20080036652A1
公开(公告)日：2008-02-14
申请号：US11640337
申请日：2006-12-18
申请人： Michael Shore , Benjamin Dolgin , Steven Cotten
发明人： Michael Shore , Benjamin Dolgin , Steven Cotten
IPC分类号： G01S5/16 , G01S1/70 , H04B7/185
CPC分类号： G01C15/00 , E21B47/02224
摘要： A positioning system designed to provide a three dimensional location of an object. The system can include one or more multiple transmitters or electromagnetic beacons, software defined radio receivers with an associated processing unit and data acquisition system, and magnetic antennas. The system applies theoretical calculations, scale model testing, signal processing, and sensor data to operate.
摘要翻译：设计用于提供物体的三维位置的定位系统。该系统可以包括一个或多个多个发射机或电磁信标，具有相关联的处理单元和数据采集系统的软件定义的无线电接收机以及磁性天线。该系统应用理论计算，尺度模型测试，信号处理和传感器数据进行操作。

3. 发明申请

US20070115711A1 Device and method for using dynamic cell plate sensing in a DRAM memory cell 有权
标题翻译：在DRAM存储单元中使用动态单元板感测的装置和方法
公开(公告)号：US20070115711A1
公开(公告)日：2007-05-24
申请号：US11653590
申请日：2007-01-16
申请人： Michael Shore , Brian Callaway
发明人： Michael Shore , Brian Callaway
IPC分类号： G11C5/06
CPC分类号： G11C11/4074 , H01L27/0207 , H01L27/108 , H01L27/10852 , H01L27/10873
摘要： A memory cell, device, system and method for operating a memory cell are disclosed that utilize an isolated dynamic cell plate. The memory cell includes a first and second pass transistor and a first and second capacitor. The first pass transistor and first capacitor and the second pass transistor and second capacitor are each configured in series for individual respective coupling between a first digit line and a second digit line. The first and second pass transistors are further configured for respective control by first and second wordlines. The memory cell further includes an interconnection formed on a cell plate conductor between a terminal end of the first capacitor and a terminal end of the second capacitor. Furthermore, the interconnection is electrically isolated from other portions of the cell plate conductor.
摘要翻译：公开了一种用于操作存储器单元的存储器单元，器件，系统和方法，其利用隔离的动态单元板。存储单元包括第一和第二传输晶体管以及第一和第二电容器。第一传输晶体管和第一电容器以及第二传输晶体管和第二电容器各自被配置为串联地用于第一数字线和第二数字线之间的各自的耦合。第一和第二传输晶体管被进一步配置用于由第一和第二字线进行相应的控制。存储单元还包括在第一电容器的末端和第二电容器的末端之间的单元板导体上形成的互连。此外，互连与电池板导体的其它部分电绝缘。

4. 发明申请

US20060203599A1 Detection of row-to-row shorts and other row decode defects in memory devices 有权
公开(公告)号：US20060203599A1
公开(公告)日：2006-09-14
申请号：US11078764
申请日：2005-03-11
申请人： Daniel Doyle , Michael Shore
发明人： Daniel Doyle , Michael Shore
IPC分类号： G11C8/00
CPC分类号： G11C29/024 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver. The test signal, when latched, may limit the Vccp current (by generating VccpRDec) to the row to be tested so as to detect row-to-row shorts without disturbing the VNWL (negative wordline voltage) and to reduce unnecessary stress and the P-channel breakdown in the row decodes during burn-in testing of a memory chip. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

5. 发明授权

US6104650A Sacrifice read test mode 有权
公开(公告)号：US6104650A
公开(公告)日：2000-08-15
申请号：US350602
申请日：1999-07-09
申请人： Michael Shore
发明人： Michael Shore
IPC分类号： G11C29/24 , G11C29/50 , G11C13/00
CPC分类号： G11C29/50 , G11C29/24 , G11C11/401
摘要： Testing methods and facilitating circuitry to permit activation and latching of multiple word lines in a dynamic memory device in conjunction with external control over digit line equilibrate and activation of sense amplifiers. Such testing methods are adaptable for use prior to row repair or post row repair. Such testing methods permit controlled stressing of cell margin and beta ratio by selective coupling of one or more sacrificial rows to a digit line prior to sensing of data in a target row. Useful design and reliability information may be obtained through application of various embodiments of such testing methods.

6. 发明授权

US5895962A Structure and a method for storing information in a semiconductor device 失效
标题翻译：用于在半导体器件中存储信息的结构和方法
公开(公告)号：US5895962A
公开(公告)日：1999-04-20
申请号：US664109
申请日：1996-06-13
申请人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
发明人： Hua Zheng , Michael Shore , Jeffrey P. Wright , Todd A. Merritt
IPC分类号： G01R31/3181 , G11C17/10 , H01L27/112 , H01L27/04 , G11C17/00
CPC分类号： G01R31/3181 , G11C17/10 , H01L27/112
摘要： A semiconductor device includes a plurality of conductive layers that are formed on the substrate. Two electrically intercoupled sections of a read-only storage element, such as a fuse element, which together compose the storage element, are each formed in a different one of the conductive layers. The storage element has a storage state, and each section has a conductivity. One can change the storage state of the storage element by changing the conductivity of one of the sections. Additionally, multiple storage elements may be coupled in parallel to form a storage module. Each of the storage elements of the storage module may include multiple storage sections that are each formed in a different conductive layer. The storage elements may store the version number of the mask set used to form the semiconductor device. Alternatively, a conductive layer is formed on a substrate, and one or more read-only storage elements are formed in the conductive layer. Each of the storage elements is formed in a predetermined state such that they collectively store a digital value that identifies a mask used to form the conductive layer.
摘要翻译：半导体器件包括形成在衬底上的多个导电层。共同组成存储元件的只读存储元件（例如熔丝元件）的两个电互相耦合部分分别形成在不同的一个导电层中。存储元件具有存储状态，并且每个部分具有导电性。可以通过改变其中一个部分的电导率来改变存储元件的存储状态。另外，多个存储元件可以并联耦合以形成存储模块。存储模块的每个存储元件可以包括各自形成在不同导电层中的多个存储部分。存储元件可以存储用于形成半导体器件的掩模集的版本号。或者，在衬底上形成导电层，并且在导电层中形成一个或多个只读存储元件。每个存储元件形成为预定状态，使得它们共同地存储识别用于形成导电层的掩模的数字值。

7. 发明申请

US20080074934A1 Detection of row-to-row shorts and other row decode defects in memory devices 有权
标题翻译：检测存储器件中的行到行短路和其他行解码缺陷
公开(公告)号：US20080074934A1
公开(公告)日：2008-03-27
申请号：US11986235
申请日：2007-11-20
申请人： Daniel Doyle , Michael Shore
发明人： Daniel Doyle , Michael Shore
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C29/024 , G11C29/02 , G11C29/025 , G11C2029/1202
摘要： A system and method to detect row-to-row shorts and other row decode defects in memory devices and other electronic devices having a similar data storage functionality is disclosed. A selective switching between a normal large pull-up device and a smaller one in a wordline driver path allows limiting the current in the pull-up circuit to a low value so as to detect shorts because the shorts will cause the active wordline voltage level to drop, while a wordline without shorts will operate well. A GIDL (Gate Induced Drain Leakage) reduction circuit may be used as a pull-up circuit connected to supply a bias voltage to the wordline driver associated with a wordline being tested for shorts or other defects. A test signal may be selectively generated during testing so as to supply a lower strength voltage output of the GIDL circuit (the VccpRDec output) as the bias voltage to the wordline driver. The test signal, when latched, may limit the Vccp current (by generating VccpRDec) to the row to be tested so as to detect row-to-row shorts without disturbing the VNWL (negative wordline voltage) and to reduce unnecessary stress and the P-channel breakdown in the row decodes during burn-in testing of a memory chip. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
摘要翻译：公开了一种用于检测具有相似数据存储功能的存储器件和其他电子设备中的行到行短路和其他行解码缺陷的系统和方法。在正常的大上拉器件和字线驱动器通路中的较小的上拉器件之间的选择性切换允许将上拉电路中的电流限制为低值，以便检测短路，因为短路将使有源字线电压电平而没有短裤的字线将运行良好。可以使用GIDL（栅极引入漏极泄漏）还原电路作为上拉电路，其连接到与被测试的短路或其他缺陷的字线相关联的字线驱动器。可以在测试期间选择性地产生测试信号，以便将GIDL电路的较低强度电压输出（VccpRDec输出）作为偏置电压提供给字线驱动器。当锁存时，测试信号可能会将Vccp电流（通过产生VccpRDec）限制到要测试的行，以便在不干扰VNWL（负字线电压）的情况下检测行到行的短路，并减少不必要的应力，而P 在存储器芯片的老化测试期间，行中的通道故障解码。由于管理摘要的规则，本摘要不应用于解释索赔。

8. 发明授权

US07251173B2 Combination column redundancy system for a memory array 有权
标题翻译：存储阵列的组合列冗余系统
公开(公告)号：US07251173B2
公开(公告)日：2007-07-31
申请号：US11195878
申请日：2005-08-02
申请人： Aron Lunde , Michael Shore
发明人： Aron Lunde , Michael Shore
IPC分类号： G11C7/00
CPC分类号： G11C29/81 , G11C29/808 , G11C29/846
摘要： A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.
摘要翻译：列冗余系统组合至少两个不同的冗余系统，以提供本地冗余存储器和共享冗余存储器。列冗余系统包括多组本地冗余列存储器，每组存储器的本地冗余列与多个存储器子阵列中的相应一个存储器子阵列相关联。存储器组的本地冗余列的存储器列适于替换相应存储器子阵列的存储器的有缺陷的列。列冗余系统还包括适于替换多个存储器子阵列的存储器的有缺陷的列的共享冗余存储器列。

9. 发明授权

US06947346B2 Reducing digit equilibrate current during self-refresh mode 有权
标题翻译：在自刷新模式下减少数字平衡电流
公开(公告)号：US06947346B2
公开(公告)日：2005-09-20
申请号：US10768829
申请日：2004-01-30
申请人： Michael Shore , Brian P. Callaway
发明人： Michael Shore , Brian P. Callaway
IPC分类号： G11C7/12 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40618 , G11C7/12 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.
摘要翻译：数字平衡电流在自刷新模式下通过减少易失性存储器中的子阵列预充电使泄放装置启用的时间减少。所选择的子阵列被预先充电，在使给定行的存储器单元刷新之前使能一个周期的放电器件。自动刷新计数器和行地址块用于生成要刷新的存储单元的段地址和行地址。每个子阵列在给定子阵列中的另一行存储器单元被刷新之前具有刷新的给定行存储器单元。

10. 发明授权

US06711093B1 Reducing digit equilibrate current during self-refresh mode 有权
标题翻译：在自刷新模式下减少数字平衡电流
公开(公告)号：US06711093B1
公开(公告)日：2004-03-23
申请号：US10232739
申请日：2002-08-29
申请人： Michael Shore , Brian P. Callaway
发明人： Michael Shore , Brian P. Callaway
IPC分类号： G11C800
CPC分类号： G11C11/40618 , G11C7/12 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a given row of memory cells refreshed. An auto-refresh counter and row address block are used to generate a section address and a row address of memory cells to refresh. Each sub-array has a given row of memory cells refreshed before another row of memory cells in a given sub-array is refreshed.
摘要翻译：数字平衡电流在自刷新模式下通过减少易失性存储器中的子阵列预充电使泄放装置启用的时间减少。所选择的子阵列被预先充电，在使给定行的存储器单元刷新之前使能一个周期的放电器件。自动刷新计数器和行地址块用于生成要刷新的存储单元的段地址和行地址。每个子阵列在给定子阵列中的另一行存储器单元被刷新之前具有刷新的给定行存储器单元。

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