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1. 发明申请

US20080256551A1 System and Method For Storing State Information 审中-公开
标题翻译：用于存储状态信息的系统和方法
公开(公告)号：US20080256551A1
公开(公告)日：2008-10-16
申请号：US12067587
申请日：2005-09-21
申请人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
发明人： Michael Priel , Dan Kuzmin , Leonid Smolyansky
IPC分类号： G06F9/46
CPC分类号： G06F9/462
摘要： A method for storing state information, the method includes storing, at a first circuit, state information representative of a state of a second circuit while the second circuit enters a low power mode; characterized by receiving an indication that a task switching from a first task to a second task should occur; storing a state information representative of a state of the second circuit, at the first circuit; receiving an indication that the first task should be resumed; and writing the stored state information from the first circuit to the second circuit. A system includes a first circuit and a second circuit, whereas the first circuit is connected to the second circuit and is adapted to store state information representative of a state of a second circuit; characterized by including a controller adapted to control a storage of the state information if at least a portion of the second circuit is powered down or if the second circuit is associated with a task switching operation.
摘要翻译：一种用于存储状态信息的方法，所述方法包括在第一电路处存储表示第二电路的状态的状态信息，同时第二电路进入低功率模式; 其特征在于接收从第一任务切换到第二任务的任务应发生的指示; 在所述第一电路处存储表示所述第二电路的状态的状态信息; 收到第一个任务应恢复的指示; 以及将所存储的状态信息从第一电路写入第二电路。一种系统包括第一电路和第二电路，而第一电路连接到第二电路，并适于存储表示第二电路的状态的状态信息; 其特征在于包括控制器，其适于在所述第二电路的至少一部分断电或者所述第二电路与任务切换操作相关联时控制所述状态信息的存储。

2. 发明申请

US20140325183A1 INTEGRATED CIRCUIT DEVICE, ASYMMETRIC MULTI-CORE PROCESSING MODULE, ELECTRONIC DEVICE AND METHOD OF MANAGING EXECUTION OF COMPUTER PROGRAM CODE THEREFOR 审中-公开
标题翻译：集成电路设备，不对称多核处理模块，电子设备及其计算机程序代码的执行方法
公开(公告)号：US20140325183A1
公开(公告)日：2014-10-30
申请号：US14358053
申请日：2011-11-28
申请人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Dan Kuzmin , Michael Priel , Leonid Smolyansky
IPC分类号： G06F15/76
CPC分类号： G06F15/76 , G06F9/5083 , G06F9/5094 , G06F2015/765 , Y02D10/22
摘要： An asymmetric multi-core processing module is described. The asymmetric multi-core processing module comprises at least one processing core of a first type, at least one processing core of at least one further type, and at least one core identifier configuration component. The at least one core identifier configuration component is arranged to enable dynamic configuration of a value of a core identifier of at least one of the processing cores of the first and at least one further types.
摘要翻译：描述了一种非对称多核处理模块。非对称多核处理模块包括至少一个第一类型的处理核心，至少一个另外类型的至少一个处理核心和至少一个核心标识符配置组件。至少一个核心标识符配置组件被布置成使得能够动态地配置第一和至少一个其它类型的至少一个处理核心的核心标识符的值。

3. 发明申请

US20130124800A1 APPARATUS AND METHOD FOR REDUCING PROCESSOR LATENCY 审中-公开
标题翻译：减少处理器延迟的装置和方法
公开(公告)号：US20130124800A1
公开(公告)日：2013-05-16
申请号：US13812168
申请日：2010-07-27
申请人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyansky
发明人： Michael Priel , Dan Kuzmin , Anton Rozen , Leonid Smolyansky
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0804 , G06F12/0811 , G06F12/0877 , G06F13/28
摘要： There is provided a data processing system comprising a central processing unit, a processor cache memory operably coupled to the central processing unit and an external connection operably coupled to the central processing unit and processor cache memory in which a portion of the data processing system is arranged to load data directly from the external connection into the processor cache memory and modify a source address of said directly loaded data. There is also provided a method of improving latency in a data processing system having a central processing unit operably coupled to a processor cache memory and an external connection operably coupled to the central processing unit and processor cache memory, comprising loading data directly from the external connection into the processor cache memory and modifying a source address for said data to become indicative of a location other than from the external connection.
摘要翻译：提供了一种数据处理系统，包括中央处理单元，可操作地耦合到中央处理单元的处理器高速缓冲存储器和可操作地耦合到中央处理单元和处理器高速缓存存储器的外部连接，其中数据处理系统的一部分被布置将数据直接从外部连接加载到处理器高速缓冲存储器中，并修改所述直接加载数据的源地址。还提供了一种改进数据处理系统中的等待时间的方法，该系统具有可操作地耦合到处理器高速缓冲存储器的中央处理单元和可操作地耦合到中央处理器和处理器高速缓存存储器的外部连接，包括直接从外部连接进入处理器高速缓冲存储器并修改所述数据的源地址以变成指示来自外部连接的位置。

4. 发明授权

US07733117B1 Method for protecting a security real time clock generator and a device having protection capabilities 有权
标题翻译：用于保护安全实时时钟发生器和具有保护能力的设备的方法
公开(公告)号：US07733117B1
公开(公告)日：2010-06-08
申请号：US11942799
申请日：2007-11-20
申请人： Michael Priel , Leonid Smolyansky , Dan Kuzmin
发明人： Michael Priel , Leonid Smolyansky , Dan Kuzmin
IPC分类号： H03K19/00 , G06F11/30
CPC分类号： G06F21/554 , G06F1/14 , G06F21/86 , H03K2217/0054
摘要： A device having protection capabilities, the device includes a voltage supply unit that is connected to an integrated circuit and provides a supply voltage to the integrated circuit; wherein the integrated circuit includes: a security real time clock generator that includes an input; a masking unit that is connected to the input, wherein the masking unit isolates the input when a voltage supply monitor is disabled; and wherein the voltage supply monitor monitors the voltage supply unit and wherein a change in a level of supply voltage affects a level of a signal provided to the input.
摘要翻译：一种具有保护能力的装置，该装置包括连接到集成电路并向集成电路提供电源电压的电压供应单元; 其中所述集成电路包括：安全实时时钟发生器，其包括输入; 连接到输入的屏蔽单元，其中当电压供应监视器被禁用时，所述屏蔽单元隔离所述输入; 并且其中所述电压供应监视器监视所述电压供应单元，并且其中电源电压电平的变化影响提供给所述输入的信号的电平。

5. 发明授权

US09368162B2 Integrated circuit device, power management module and method for providing power management 有权
标题翻译：集成电路器件，电源管理模块及提供电源管理的方法
公开(公告)号：US09368162B2
公开(公告)日：2016-06-14
申请号：US13983145
申请日：2011-02-08
申请人： Michael Priel , Dan Kuzmin , Sergey Sofer
发明人： Michael Priel , Dan Kuzmin , Sergey Sofer
IPC分类号： G11C5/14 , G06F1/32
CPC分类号： G11C5/14 , G06F1/3225 , G06F1/3275 , Y02D10/14 , Y02D50/20
摘要： An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.
摘要翻译：一种集成电路装置，包括至少一个包括多个存储器子模块的存储器模块，以及至少一个功率管理模块，被布置成为所述至少一个存储器模块提供功率管理。所述至少一个电源管理模块被布置成确定至少一个存储器子模块的内容何时是冗余的，并且在确定所述至少一个存储器的内容之后将所述至少一个存储器子模块置于掉电状态子模块是多余的。

6. 发明授权

US09354645B2 Voltage regulating circuit with selectable voltage references and method therefor 有权
标题翻译：具有可选电压参考的电压调节电路及其方法
公开(公告)号：US09354645B2
公开(公告)日：2016-05-31
申请号：US14115223
申请日：2011-05-27
申请人： Michael Priel , Dan Kuzmin , Sergey Sofer
发明人： Michael Priel , Dan Kuzmin , Sergey Sofer
IPC分类号： G05F1/56 , G05F1/46 , G05F1/563 , H02M1/00
CPC分类号： G05F1/468 , G05F1/465 , G05F1/56 , G05F1/563 , H02M2001/0025 , Y10T307/406
摘要： A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.
摘要翻译：提供电压调节电路，用于调节输出电压，以使所述输出电压的电平和参考电平之间的绝对差最小化。电压调节电路包括电压调节器和参考电平发生器。参考电平发生器基于所述输出电压电平和所述参考电平产生内部参考电平，使得所述内部参考电平不超过所述输出电压电平超过允许的最大增量。电压调节器调节所述输出电压，以便最小化所述输出电压电平和所述内部参考电平之间的绝对差。还公开了一种调节输出电压的方法。

7. 发明申请

US20150206559A1 REGISTER FILE MODULE AND METHOD THEREFOR 有权
标题翻译：寄存器文件模块及其方法
公开(公告)号：US20150206559A1
公开(公告)日：2015-07-23
申请号：US14415153
申请日：2012-07-20
申请人： Michael Priel , Leonid Fleshel , Dan Kuzmin
发明人： Michael Priel , Leonid Fleshel , Dan Kuzmin
IPC分类号： G11C7/10 , G11C7/06
CPC分类号： G11C7/1072 , G11C7/065 , G11C7/1039 , G11C7/22 , G11C19/00 , G11C19/28 , G11C29/32 , G11C2207/007
摘要： A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.
摘要翻译：描述了包括至少一个包括多个锁存装置的寄存器阵列的寄存器文件模块。多个锁存装置被布置为当寄存器文件模块被配置为在第一功能操作模式下操作时，分别提供存储器位单元，并且至少一个时钟控制部件被布置成接收时钟信号并传播时钟信号到至少一个寄存器阵列内的锁存器件。寄存器文件模块可配置为以第二扫描模式操作，其中至少一个寄存器阵列内的锁存器件被布置成至少一个扫描链。所述至少一个时钟控制部件布置成将所述时钟信号传播到所述至少一个寄存器阵列内的锁存器件，使得所述至少一个扫描链内的另外的锁存器件接收所述时钟信号的反相形式。

8. 发明申请

US20150162818A1 SYSTEM ON A CHIP, APPARATUS AND METHOD FOR VOLTAGE RIPPLE REDUCTION ON A POWER SUPPLY LINE OF AN INTEGRATED CIRCUIT DEVICE OPERABLE IN AT LEAST TWO MODES 有权
标题翻译：一种芯片上的系统，用于在两种模式下操作的集成电路装置的电源线上的电压纹波减少的装置和方法
公开(公告)号：US20150162818A1
公开(公告)日：2015-06-11
申请号：US14415611
申请日：2012-07-19
申请人： Michael Priel , Dan Kuzmin , Sergey Sofer
发明人： Michael Priel , Dan Kuzmin , Sergey Sofer
IPC分类号： H02M1/15 , G05F1/613
CPC分类号： H02M1/15 , G05F1/613 , G06F1/26 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： An apparatus for voltage ripple reduction on a power supply line of an integrated circuit device is provided to be operable in at least two modes. The apparatus includes: one or more clamping devices connectable to the power supply line; a clamp control unit; and a mode change detection unit arranged to monitor an interface of the integrated circuit device for one or more information indicating an upcoming mode change of the integrated circuit device and to provide a mode change signal to the clamp control unit when the one or more information is detected. The clamp control unit is arranged to connect at least one of the one or more clamping devices to the power supply line when receiving the mode change signal.
摘要翻译：提供了一种用于集成电路器件的电源线上的电压纹波降低的装置，以至少两种模式可操作。该装置包括：可连接到电源线的一个或多个夹紧装置; 夹具控制单元; 以及模式改变检测单元，被配置为监视集成电路装置的接口，用于指示集成电路装置的即将到来的模式改变的一个或多个信息，并且当所述一个或多个信息是检测到。钳位控制单元被布置成当接收到模式改变信号时，将一个或多个钳位装置中的至少一个连接到电源线。

9. 发明授权

US09000804B2 Integrated circuit device comprising clock gating circuitry, electronic device and method for dynamically configuring clock gating 有权
标题翻译：集成电路装置，包括时钟选通电路，用于动态配置时钟门控的电子装置和方法
公开(公告)号：US09000804B2
公开(公告)日：2015-04-07
申请号：US13580583
申请日：2010-03-03
申请人： Michael Priel , Ilan Kapilushnik , Dan Kuzmin
发明人： Michael Priel , Ilan Kapilushnik , Dan Kuzmin
IPC分类号： H03K19/00 , G06F1/32
CPC分类号： H03K19/0016 , G06F1/3237 , Y02D10/128
摘要： An integrated circuit comprises clock gating circuitry comprising at least one gating component located within a clock distribution network and arranged to enable at least one part of the clock distribution network to be gated, and gating control circuitry arranged to cause the at least one gating component to disable the at least one part of the clock distribution network upon certain conditions being fulfilled. The clock gating circuitry further comprises clock gating disabling circuitry configurable to enable the gating of the at least one part of the clock distribution network to be disabled.
摘要翻译：集成电路包括时钟门控电路，其包括位于时钟分配网络内的至少一个选通组件，并且被布置为使得能够门控时钟分配网络的至少一部分;以及门控控制电路，其被布置成使至少一个门控组件在满足某些条件的情况下禁用时钟分配网络的至少一部分。时钟选通电路还包括时钟门控禁用电路，其可配置为使得能够禁止时钟分配网络的至少一个部分的选通。

10. 发明授权

US08850232B2 Method for protecting a cryptographic module and a device having cryptographic module protection capabilities 有权
标题翻译：用于保护加密模块的方法和具有加密模块保护能力的设备
公开(公告)号：US08850232B2
公开(公告)日：2014-09-30
申请号：US12919541
申请日：2008-03-19
申请人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
IPC分类号： G06F12/14 , G08B29/00 , G06F21/55 , G06F21/86
CPC分类号： G06F21/558 , G06F21/554 , G06F21/755 , G06F21/86
摘要： A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
摘要翻译：一种用于保护密码模块的设备和方法，该方法包括：当物理参数具有与加密模块正常工作的标称参数值不同的第一值时，估计适于故障的电路的功能。当物理参数具有与标称参数值不同的第二值并且第一值和标称参数值之间的差小于第二值和标称参数值之间的差时，加密模块发生故障。如果估计电路发生故障，则应用加密模块保护措施。

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