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1. 发明申请

US20140155027A1 ELECTRONIC DEVICE AND A COMPUTER PROGRAM PRODUCT 有权
标题翻译：电子设备和计算机程序产品
公开(公告)号：US20140155027A1
公开(公告)日：2014-06-05
申请号：US14233185
申请日：2011-08-09
申请人： Michael Priel , Evgeny Margolis , Anton Rozen
发明人： Michael Priel , Evgeny Margolis , Anton Rozen
IPC分类号： H04W12/08
CPC分类号： H04W12/08 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F21/10 , G06F21/554 , G06F21/81 , G06F2221/2105 , G06F2221/2141 , Y02D10/171
摘要： An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.
摘要翻译：电子设备包括被安排为存储安全数据的安全模块。安全模块外部的组件具有正常工作模式，具有正常模式工作电压。布置了一个接口来提供对安全模块的访问。电压监视单元连接到部件并且被布置成监视部件的工作电压Vsup。接口控制单元连接到电压监视单元和接口。接口控制单元被布置成当工作电压低于预定安全存取电压电平时，通过接口禁止对安全模块的访问，安全访问电压高于正常模式工作电压。

2. 发明授权

US09510200B2 Electronic device and a computer program product 有权
标题翻译：电子设备和计算机程序产品
公开(公告)号：US09510200B2
公开(公告)日：2016-11-29
申请号：US14233185
申请日：2011-08-09
申请人： Michael Priel , Evgeny Margolis , Anton Rozen
发明人： Michael Priel , Evgeny Margolis , Anton Rozen
IPC分类号： H04W12/08 , G06F21/10 , G06F21/55 , G06F21/81 , G06F1/32
CPC分类号： H04W12/08 , G06F1/3237 , G06F1/3287 , G06F1/3296 , G06F21/10 , G06F21/554 , G06F21/81 , G06F2221/2105 , G06F2221/2141 , Y02D10/171
摘要： An electronic device comprises a secured module arranged to store secured data. A component outside the secured module has a normal operating mode with a normal mode operating voltage. An interface is arranged to provide access to the secured module. A voltage monitoring unit is connected to the component and arranged to monitor an operating voltage Vsup of the component. An interface control unit is connected to the voltage monitoring unit and the interface. The interface control unit is arranged to inhibit access to the secured module through the interface when the operating voltage is below a predetermined secure access voltage level, the secure access voltage being higher than the normal mode operating voltage.
摘要翻译：电子设备包括被安排为存储安全数据的安全模块。安全模块外部的组件具有正常工作模式，具有正常模式工作电压。布置了一个接口来提供对安全模块的访问。电压监视单元连接到部件并且被布置成监视部件的工作电压Vsup。接口控制单元连接到电压监视单元和接口。接口控制单元被布置成当工作电压低于预定安全存取电压电平时，通过接口禁止对安全模块的访问，安全访问电压高于正常模式工作电压。

3. 发明授权

US08850232B2 Method for protecting a cryptographic module and a device having cryptographic module protection capabilities 有权
标题翻译：用于保护加密模块的方法和具有加密模块保护能力的设备
公开(公告)号：US08850232B2
公开(公告)日：2014-09-30
申请号：US12919541
申请日：2008-03-19
申请人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Asaf Ashkenazi , Dan Kuzmin , Anton Rozen
IPC分类号： G06F12/14 , G08B29/00 , G06F21/55 , G06F21/86
CPC分类号： G06F21/558 , G06F21/554 , G06F21/755 , G06F21/86
摘要： A device and a method for protecting a cryptographic module of which the method includes: estimating a functionality of a circuit that is adapted to malfunction when a physical parameter has a first value different from a nominal parameter value at which the cryptographic module functions correctly. The cryptographic module malfunctions when the physical parameter has a second value different from the nominal parameter value and a difference between the first value and the nominal parameter value being smaller than a difference between the second value and the nominal parameter value. A cryptographic module protective measure is applied if estimating that the circuit malfunctions.
摘要翻译：一种用于保护密码模块的设备和方法，该方法包括：当物理参数具有与加密模块正常工作的标称参数值不同的第一值时，估计适于故障的电路的功能。当物理参数具有与标称参数值不同的第二值并且第一值和标称参数值之间的差小于第二值和标称参数值之间的差时，加密模块发生故障。如果估计电路发生故障，则应用加密模块保护措施。

4. 发明授权

US08598949B2 Electronic circuit and method for state retention power gating 有权
标题翻译：电子电路和状态保持电源门控方法
公开(公告)号：US08598949B2
公开(公告)日：2013-12-03
申请号：US13634730
申请日：2010-06-11
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G05F1/10
CPC分类号： H03K3/00 , H03K3/012 , H03K19/0008
摘要： A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.
摘要翻译：一种方法和电子电路，所述方法包括：向切换电路发送状态保持电源选通（SRPG）电路和向第一电源发送指示SRPG电路应以功能模式工作的控制信号; 由开关电路将第三电网耦合到第一电网; 通过第一电网，开关电路和第三电网从第一电源向SRPG电路供电; 经由第二电网从第二电源向第二电路供电; 向SRPG电路和第一电源发送指示SRPG电路在状态保持模式下工作的控制信号; 由开关电路将第三电网耦合到第二电网; 通过第二电网，开关电路和第三电网从第二电源向SRPG电路供电; 经由所述第二电网从所述第二电源向所述第二电路供电; 并通过SRPG状态信息存储。

5. 发明申请

US20130097449A1 MEMORY UNIT, INFORMATION PROCESSING DEVICE, AND METHOD 有权
标题翻译：存储单元，信息处理设备和方法
公开(公告)号：US20130097449A1
公开(公告)日：2013-04-18
申请号：US13634755
申请日：2010-06-11
申请人： Michael Priel , Joseph Rabinowicz , Anton Rozen
发明人： Michael Priel , Joseph Rabinowicz , Anton Rozen
IPC分类号： G06F1/32 , G11C5/14
CPC分类号： G06F1/3287 , G11C5/148 , G11C7/20
摘要： A memory unit comprises at least two volatile memory elements, analyzing circuitry and power gate. The memory elements may for example be latches, flip-flops, or registers. Each of the memory elements has at least two different states including a predefined reset state. The analyzing circuitry generates a power-down enable signal in response to each of the memory elements being in its reset state. The power gate powers down the memory elements in response to the power-down enable signal. The memory elements may be arranged to assume their reset states upon powering up the memory unit.
摘要翻译：存储器单元包括至少两个易失性存储元件，分析电路和功率门。存储器元件可以例如是锁存器，触发器或寄存器。每个存储元件具有至少两个不同的状态，包括预定义的复位状态。分析电路响应于每个存储器元件处于其复位状态而产生掉电使能信号。功率门响应于掉电使能信号而关断存储器元件。存储器元件可以被布置成在给存储器单元加电时采取它们的复位状态。

6. 发明申请

US20120239960A1 METHOD FOR COMPENSATING A TIMING SIGNAL, AN INTEGRATED CIRCUIT AND ELECTRONIC DEVICE 有权
标题翻译：用于补偿定时信号，集成电路和电子设备的方法
公开(公告)号：US20120239960A1
公开(公告)日：2012-09-20
申请号：US13510103
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G11C7/1051 , G11C7/1066
摘要： A method for compensating a timing signal with which an outputting of data states of at least one data signal is synchronised. The method comprises receiving a current set of data states and a next set of data states, identifying state transitions between the current set of data states and the next set of data states, determining an amount of compensation to apply to the timing signal based at least partly on the state transitions identified between the current set of data states and the next set of data states, and applying the determined amount of compensation to the timing signal such that the compensation applies to the outputting of the next set of data states.
摘要翻译：一种用于补偿定时信号的方法，其中至少一个数据信号的数据状态的输出被同步。该方法包括：接收当前的一组数据状态和下一组数据状态，识别当前数据状态集合与下一组数据状态之间的状态转换，至少至少确定应用于定时信号的补偿量部分地基于在当前数据状态集合和下一组数据状态之间识别的状态转换，以及将确定的补偿量应用于定时信号，使得补偿适用于输出下一组数据状态。

7. 发明申请

US20120236630A1 BYPASS CAPACITOR CIRCUIT AND METHOD OF PROVIDING A BYPASS CAPACITANCE FOR AN INTEGRATED CIRCUIT DIE 有权
标题翻译：旁路电容器电路和为集成电路提供旁路电容的方法
公开(公告)号：US20120236630A1
公开(公告)日：2012-09-20
申请号：US13509922
申请日：2009-11-30
申请人： Michael Priel , Leonid Fleshel , Anton Rozen
发明人： Michael Priel , Leonid Fleshel , Anton Rozen
IPC分类号： G11C11/24 , H01L21/02 , H01L27/108
CPC分类号： H01L23/5223 , G11C2029/5002 , H01L22/14 , H01L22/22 , H01L23/49589 , H01L23/5286 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A bypass capacitor circuit for an integrated circuit (IC) comprises one or more capacitive devices, each arranged in a segment of a seal ring area of a die, which comprises the IC. A method of providing a bypass capacitance for an IC comprises providing a semiconductor wafer device comprising a plurality of dies, each comprising an IC; arranging one or more capacitive devices in a seal ring area of at least one of the IC; dicing the semiconductor wafer device; in a test mode, for each of the one or more capacitive devices, enabling the capacitive device, determining an operability parameter value indicative of an operability of the capacitive device, and storing the operability parameter in a memory device; and in a normal operation mode, providing a bypass capacitance to the IC depending on a capacitance of one or more of the capacitive devices having an associated operability parameter value indicative of a non-defectiveness of the corresponding capacitive device.
摘要翻译：用于集成电路（IC）的旁路电容器电路包括一个或多个电容性器件，每个电容器件布置在包括IC的管芯的密封环区域的段中。提供用于IC的旁路电容的方法包括提供包括多个芯片的半导体晶片装置，每个芯片包括IC; 在所述IC中的至少一个的密封环区域中布置一个或多个电容性装置; 切割半导体晶片器件; 在测试模式中，对于所述一个或多个电容性装置中的每一个，启用所述电容性装置，确定指示所述电容性装置的可操作性的可操作性参数值，以及将所述可操作性参数存储在存储装置中; 并且在正常操作模式中，根据具有指示对应的电容性器件的非缺陷性的相关联的可操作性参数值的一个或多个电容器件的电容，向IC提供旁路电容。

8. 发明申请

US20120032719A1 ELECTRONIC CIRCUIT AND METHOD FOR OPERATING A MODULE IN A FUNCTIONAL MODE AND IN AN IDLE MODE 有权
标题翻译：用于在功能模式和空闲模式下操作模块的电子电路和方法
公开(公告)号：US20120032719A1
公开(公告)日：2012-02-09
申请号：US12850650
申请日：2010-08-05
申请人： Michael Priel , Anton Rozen , Yaakov Seidenwar
发明人： Michael Priel , Anton Rozen , Yaakov Seidenwar
IPC分类号： H03K3/02
CPC分类号： H03K3/0375
摘要： A method and an electronic circuit, the electronic circuit includes: a module that comprises multiple flip-flops and a control signal providing circuit; a power management circuit arranged to provide to the module a supply voltage of a functional level when the module is in a functional mode, and to provide to the module a supply voltage of an idle level when the module is in an idle mode; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the functional mode, a control signal that facilitates a state change of each of the multiple flip-flops; wherein the control signal providing circuit is arranged to provide to the multiple flip-flops, when the module is in the idle mode, a control signal that prevents a state change of each of the multiple flip-flops; wherein the each of the control signal providing circuit and a plurality of flip-flops of the multiple flip-flops comprises at least one hybrid circuit that comprises a low-threshold transistor that is coupled in parallel to at least one high-threshold transistor; wherein each hybrid circuit is arranged to maintain information or a control signal when provided with the supply voltage of the idle level; and wherein high-threshold transistors of each hybrid circuit are arranged to maintain information or a control signal when provided with a supply voltage of a level that is higher than the idle level.
摘要翻译：一种方法和电子电路，所述电子电路包括：包括多个触发器和控制信号提供电路的模块; 电源管理电路，其布置成当模块处于功能模式时向模块提供功能级的电源电压，并且当模块处于空闲模式时向模块提供空闲电平的电源电压; 其中所述控制信号提供电路被布置为当所述模块处于所述功能模式时向所述多个触发器提供有助于所述多个触发器中的每一个的状态改变的控制信号; 其中所述控制信号提供电路被布置成当所述模块处于空闲模式时向所述多个触发器提供阻止所述多个触发器中的每一个的状态改变的控制信号; 其中所述控制信号提供电路和所述多个触发器的多个触发器中的每一个包括至少一个混合电路，其包括与至少一个高阈值晶体管并联耦合的低阈值晶体管; 其中每个混合电路被布置成在被提供有空闲电平的电源电压时保持信息或控制信号; 并且其中每个混合电路的高阈值晶体管被布置成在被提供有高于空闲电平的电平的电源电压时维持信息或控制信号。

9. 发明授权

US07941716B2 Method for race prevention and a device having race prevention capabilities 有权
标题翻译：防止竞赛的方法和具有防守能力的装置
公开(公告)号：US07941716B2
公开(公告)日：2011-05-10
申请号：US11909394
申请日：2005-03-23
申请人： Michael Priel , Dan Kuzmin , Anton Rozen
发明人： Michael Priel , Dan Kuzmin , Anton Rozen
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318541 , G01R31/318536 , H03K3/0375
摘要： A method for race prevention includes: selectively providing data or scan data to a input latching logic, activating the input latching logic for a first scan mode activation period, introducing a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating a output latching logic, connected to the input latching logic for a second scan mode activation period. A device having race prevention capabilities includes: an interface logic, a input latching logic, a output latching logic and a control logic. The interface logic is adapted to selectively provide data or scan data to the input latching logic. The control logic is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic and a start point of a second scan mode activation period of the output latching logic.
摘要翻译：一种防止竞赛的方法包括：选择性地向输入锁存逻辑提供数据或扫描数据，在第一扫描模式激活期间激活输入锁存逻辑，在第一扫描模式激活期和第二扫描模式激活之间引入实质的时间偏移并且激活输出锁存逻辑，连接到输入锁存逻辑用于第二扫描模式激活周期。具有防止竞争能力的装置包括：接口逻辑，输入锁存逻辑，输出锁存逻辑和控制逻辑。接口逻辑适于选择性地向输入锁存逻辑提供数据或扫描数据。控制逻辑适于在输入锁存逻辑的第一扫描模式激活周期的终点与输出锁存逻辑的第二扫描模式激活周期的起始点之间引入实质的时间差。

10. 发明申请

US20090177903A1 METHOD AND DEVICE FOR POWER MANAGEMENT 有权
标题翻译：用于电源管理的方法和装置
公开(公告)号：US20090177903A1
公开(公告)日：2009-07-09
申请号：US12304854
申请日：2006-06-22
申请人： Anton Rozen , Michael Priel , Leonid Smolyansky
发明人： Anton Rozen , Michael Priel , Leonid Smolyansky
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/3228 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A device and method for power management. The method includes receiving an indication about a load of a circuit, determining at least one long-term activation parameter in view of a circuit load pattern during at least one long period; determining at least one short-term activation parameter in response to an expected short period load change of the circuit; and providing least one clock signal and at least one supply voltage in response to the long-term activation parameter and in response to the short-term supply parameter.
摘要翻译：一种用于电源管理的设备和方法。该方法包括接收关于电路的负载的指示，在至少一个长时间段期间根据电路负载模式确定至少一个长期激活参数; 响应于所述电路的期望的短周期负载变化来确定至少一个短期激活参数; 以及响应于所述长期激活参数和响应于所述短期供应参数而提供至少一个时钟信号和至少一个电源电压。

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