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1. 发明授权

US08797053B2 Positioning and socketing for semiconductor dice 有权
标题翻译：半导体芯片的定位和插槽
公开(公告)号：US08797053B2
公开(公告)日：2014-08-05
申请号：US13114876
申请日：2011-05-24
申请人： Michael L. Rutigliano , Eric J. M. Moret , David Shia
发明人： Michael L. Rutigliano , Eric J. M. Moret , David Shia
IPC分类号： G01R31/00 , G01R1/073
CPC分类号： G01R1/0735 , G01R31/2891
摘要： Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.
摘要翻译：提供了用于测试裸机和封装的半导体晶片的器件和方法。随着集成电路芯片变得越来越小，并且越来越复杂，与芯片的电源和系统的其他组件的连接的接口所呈现的接口也变得越来越小，越来越复杂。本发明的实施例提供了用于细间距器件第一级互连区域的微米级精度对准能力。本发明的实施例采用空气轴承来实现被测设备的移动和对准与测试界面。另外，提供了包括由热流体支撑的膜的测试界面。

2. 发明申请

US20120299609A1 POSITIONING AND SOCKETING FOR SEMICONDUCTOR DICE 有权
标题翻译：半导体器件的定位和占有
公开(公告)号：US20120299609A1
公开(公告)日：2012-11-29
申请号：US13114876
申请日：2011-05-24
申请人： Michael L. Rutigliano , Eric J. M. Moret , David Shia
发明人： Michael L. Rutigliano , Eric J. M. Moret , David Shia
IPC分类号： G01R31/26
CPC分类号： G01R1/0735 , G01R31/2891
摘要： Devices and methods useful for testing bare and packaged semiconductor dice are provided. As integrated circuit chips become smaller and increasingly complex, the interface presented by a chip for connectivity with power supplies and other components of the system into which it is integrated similarly becomes smaller and more complex. Embodiments of the invention provide micron-scale accuracy alignment capabilities for fine pitch device first level interconnect areas. Embodiments of the invention employ air-bearings to effectuate the movement and alignment of a device under test with a testing interface. Additionally, testing interfaces comprising membranes supported by thermal fluids are provided.
摘要翻译：提供了用于测试裸机和封装的半导体晶片的器件和方法。随着集成电路芯片变得越来越小，并且越来越复杂，与芯片的电源和系统的其他组件的连接的接口所呈现的接口也变得越来越小，越来越复杂。本发明的实施例提供了用于细间距器件第一级互连区域的微米级精度对准能力。本发明的实施例采用空气轴承来实现被测设备的移动和对准与测试界面。另外，提供了包括由热流体支撑的膜的测试界面。

3. 发明申请

US20100151598A1 TEMPORARY PACKAGE FOR AT-SPEED FUNCTIONAL TEST OF SEMICONDUCTOR CHIP 有权
标题翻译：用于半导体芯片的速度功能测试的临时封装
公开(公告)号：US20100151598A1
公开(公告)日：2010-06-17
申请号：US12333842
申请日：2008-12-12
申请人： Eric J. M. Moret , Pooya Tadayon
发明人： Eric J. M. Moret , Pooya Tadayon
IPC分类号： H01L21/66 , H01L23/34
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/2886 , H01L22/14 , H01L2924/014
摘要： In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提供了用于包括高功率芯片的半导体芯片的高速功能测试的临时封装。在这方面，引入了将集成电路管芯放置在接触器层上的方法，接触器层将集成电路管芯上的触点与设计成永久地与集成电路管芯连接的多层基板上的触点电耦合，将集成散热器放置在集成电路管芯上，并将集成散热器与基板接合，将集成散热器固定在一起形成临时封装。还公开并要求保护其他实施例。

4. 发明授权

US07960190B2 Temporary package for at-speed functional test of semiconductor chip 有权
标题翻译：半导体芯片高速功能测试临时封装
公开(公告)号：US07960190B2
公开(公告)日：2011-06-14
申请号：US12333842
申请日：2008-12-12
申请人： Eric J. M. Moret , Pooya Tadayon
发明人： Eric J. M. Moret , Pooya Tadayon
IPC分类号： H01L21/66 , H01L23/34
CPC分类号： H01L22/20 , G01R31/2831 , G01R31/2886 , H01L22/14 , H01L2924/014
摘要： In some embodiments, a temporary package for at-speed functional test of semiconductor chip, including high power chips, is presented. In this regard, a method is introduced including placing an integrated circuit die on a contactor layer, the contactor layer to electrically couple contacts on the integrated circuit die with contacts on a multi-layer substrate designed to be permanently attached with the integrated circuit die, placing an integrated heat spreader over the integrated circuit die, and bonding the integrated heat spreader with the substrate, the integrated heat spreader holding the integrated circuit die in place to form a temporary package. Other embodiments are also disclosed and claimed.
摘要翻译：在一些实施例中，提供了用于包括高功率芯片的半导体芯片的高速功能测试的临时封装。在这方面，引入了将集成电路管芯放置在接触器层上的方法，接触器层将集成电路管芯上的触点与设计成永久地与集成电路管芯连接的多层衬底上的触点电耦合，将集成散热器放置在集成电路管芯上，并将集成散热器与基板接合，将集成散热器固定在一起形成临时封装。还公开并要求保护其他实施例。

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