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1. 发明授权

US06615379B1 Method and apparatus for testing a logic device 失效
标题翻译：用于测试逻辑器件的方法和装置
公开(公告)号：US06615379B1
公开(公告)日：2003-09-02
申请号：US09457255
申请日：1999-12-08
申请人： Michael J. Tripp , James W. Alexander
发明人： Michael J. Tripp , James W. Alexander
IPC分类号： G01R3128
CPC分类号： G01R31/318544 , G01R31/318502 , G01R31/318547
摘要： Method and apparatus provides for testing a device or system with a pattern generator. A series of predetermined test vectors are stored, and, for at least some of the test vectors, an associated predetermined MISR signature. A test vector is applied to a device or system under test and a gold unit in response to a gating signal, the test vector having an associated MISR determined by simulating the expected result vector. In response thereto, the gold unit and the device or system under test each produce a result vector which are compared to detect errors in the performance of the system or device under test. A MISR signature is generated for the result vector from the gold unit. The MISR signature for the result vector is then compared to the MISR associated with the input test vector. If the signatures do not match, further test vectors are prevented from being applied to the device or system under test. If the signatures match, a gating signal is provided so that additional test vectors are applied to the device or system under test.
摘要翻译：方法和装置提供了用模式发生器测试装置或系统。存储一系列预定测试向量，并且对于至少一些测试向量，存在相关联的预定MISR签名。将测试矢量应用于被测试的设备或系统，并且响应于门控信号应用金单元，测试向量具有通过模拟预期结果向量确定的相关联的MISR。作为响应，金单元和被测设备或系统都产生与被检测的系统或设备的性能中的错误进行比较的结果向量。对于金单元的结果向量生成MISR签名。然后将结果向量的MISR签名与与输入测试向量相关联的MISR进行比较。如果签名不匹配，则会阻止进一步的测试向量应用于被测设备或系统。如果签名匹配，则提供门控信号，以便将附加的测试向量应用于被测设备或系统。

2. 发明申请

US20150169224A1 EXPOSING PROTECTED MEMORY ADDRESSES 有权
标题翻译：暴露受保护的存储器地址
公开(公告)号：US20150169224A1
公开(公告)日：2015-06-18
申请号：US14109534
申请日：2013-12-17
申请人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
发明人： James W. Alexander , Devadatta V. Bodas , Muralidhar Rajappa , Ramkumar Nagappan , Andy Hoffman
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/0614 , G06F3/0622 , G06F3/0673 , G06F12/0223 , G06F12/0804 , G06F12/14 , G06F12/1425 , G06F21/74 , G06F21/79 , G06F2212/1024
摘要： Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory address may be a control register or a status register. The processing device may identify a mirror relationship between the protected memory address and an unprotected memory address and copy the data value from the protected memory address to the unprotected memory address. The unprotected memory address may be directly accessible via an external interface.
摘要翻译：提供暴露受保护的存储器地址的机制。处理设备可以将数据值存储在受保护的存储器地址处。受保护的存储器地址可以是控制寄存器或状态寄存器。处理设备可以识别受保护的存储器地址和未受保护的存储器地址之间的镜像关系，并将数据值从受保护的存储器地址复制到未受保护的存储器地址。未受保护的存储器地址可以通过外部接口直接访问。

3. 发明申请

US20140095944A1 METHOD AND APPARATUS FOR OPTIMIZING POWER AND LATENCY ON A LINK 有权
标题翻译：在链路上优化功率和延迟的方法和装置
公开(公告)号：US20140095944A1
公开(公告)日：2014-04-03
申请号：US13631934
申请日：2012-09-29
申请人： James W. Alexander , Buck W. Gremel , Pinkesh J. Shah , Malay Trivedi , Mohan K. Nair
发明人： James W. Alexander , Buck W. Gremel , Pinkesh J. Shah , Malay Trivedi , Mohan K. Nair
IPC分类号： G06F1/26 , G06F11/07
CPC分类号： G06F1/3253 , Y02D10/151
摘要： An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.
摘要翻译：公开了一种用于优化在基于处理器的系统内操作的链路的等待时间和功率的装置和方法。该装置和方法包括内置于不依赖于队列深度阈值的队列中的等待时间计。该装置和方法还包括反馈逻辑，其优化围绕增加的延迟目标的功率降低以对由链路的物理属性施加的缓慢的重新供应行为作出反应。

4. 发明申请

US20130346772A1 DYNAMIC LINK WIDTH MODULATION 有权
标题翻译：动态链路宽度调制
公开(公告)号：US20130346772A1
公开(公告)日：2013-12-26
申请号：US13532743
申请日：2012-06-25
申请人： Neven M. Abou Gazala , James W. Alexander , Devadatta V. Bodas
发明人： Neven M. Abou Gazala , James W. Alexander , Devadatta V. Bodas
IPC分类号： G06F1/32
CPC分类号： G06F1/3262 , G06F1/32 , G06F1/3206 , G06F1/3253 , G06F1/3278 , G06F11/1423 , G06F11/349 , G06F12/0831 , G06F13/1678 , G06F13/38 , G06F13/4018 , G06F13/4027 , G06F2213/0062 , H04B5/0031 , H04L12/4013 , H04L41/0896 , Y02D10/151 , Y02D10/157
摘要： Described herein are embodiments of an apparatus configured for dynamic link width modulation, a system including an apparatus configured for dynamic link width modulation, a method for dynamic link width modulation, and computer-readable media having instructions that, if executed by one or more processors, cause an apparatus to perform a dynamic link width modulation method. An apparatus configured for dynamic link width modulation may include a first counter for determining a length of a queue of packets at a source of a link, a second counter for determining a rate of utilization of the link, and a power control unit configured to modify a width of the link based at least in part on the length of the queue and the rate of utilization. Other embodiments may be described and/or claimed.
摘要翻译：这里描述的是被配置用于动态链路宽度调制的装置的实施例，包括被配置用于动态链路宽度调制的装置的系统，用于动态链路宽度调制的方法，以及具有指令的计算机可读介质，所述指令如果由一个或多个处理器使得设备执行动态链路宽度调制方法。配置用于动态链路宽度调制的装置可以包括用于确定链路源的分组队列的长度的第一计数器，用于确定链路利用率的第二计数器，以及配置为修改链路的功率控制单元链路的宽度至少部分地基于队列的长度和利用率。可以描述和/或要求保护其他实施例。

5. 发明授权

US07587625B2 Memory replay mechanism 有权
标题翻译：内存重放机制
公开(公告)号：US07587625B2
公开(公告)日：2009-09-08
申请号：US11357492
申请日：2006-02-16
申请人： James W. Alexander , Rajat Agarwal , Joaquin B. Romera
发明人： James W. Alexander , Rajat Agarwal , Joaquin B. Romera
IPC分类号： G06F11/00
CPC分类号： G06F11/141 , G06F11/106 , G06F11/1666
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for memory replay mechanisms. In some embodiments, the replay logic includes reset logic to reset at least some of the links in a point-to-point memory interconnect. In addition, the replay logic may include a replay queue to store transaction data and a replay controller to initiate a reset if the transaction data indicates a defined transaction response error. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于存储器重放机制的系统，方法和装置。在一些实施例中，重播逻辑包括复位逻辑以重置点对点存储器互连中的至少一些链路。此外，如果事务数据指示定义的事务响应错误，则重放逻辑可以包括用于存储事务数据的重播队列和重放控制器来启动复位。描述和要求保护其他实施例。

6. 发明申请

US20090172681A1 SYSTEMS, METHODS AND APPARATUSES FOR CLOCK ENABLE (CKE) COORDINATION 有权
标题翻译：用于时钟使能（CKE）协调的系统，方法和设备
公开(公告)号：US20090172681A1
公开(公告)日：2009-07-02
申请号：US11965953
申请日：2007-12-28
申请人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
发明人： James W. Alexander , Son H. Lam , Devadatta V. Bodas , Krishna Kant , Kai Cheng , Ian M. Steiner , Gopikrishna Jandhyala
IPC分类号： G06F9/46
CPC分类号： G11C7/22 , G11C7/225
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for clock enable (CKE) coordination. In some embodiments, a memory controller includes logic to predict whether a scheduled request will be issued to a rank. The memory controller may also include logic to predict whether a scheduled request will not be issued to the rank. In some embodiments, the clock enable (CKE) is asserted or de-asserted to a rank based, at least in part, on the predictions. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及用于时钟使能（CKE）协调的系统，方法和装置。在一些实施例中，存储器控制器包括用于预测排定的请求是否将被发布到等级的逻辑。存储器控制器还可以包括用于预测排定的请求是否将不被发布到等级的逻辑。在一些实施例中，时钟使能（CKE）至少部分地基于预测被断言或取消断言为等级。描述和要求保护其他实施例。

7. 发明授权

US5497456A Apparatus for transferring information between an interrupt producer and an interrupt service environment 失效
标题翻译：用于在中断产生器和中断服务环境之间传送信息的装置
公开(公告)号：US5497456A
公开(公告)日：1996-03-05
申请号：US404136
申请日：1995-03-13
申请人： James W. Alexander , Elliot Garbus , Lionel S. Smith, Jr. , Douglas D. Yoder
发明人： James W. Alexander , Elliot Garbus , Lionel S. Smith, Jr. , Douglas D. Yoder
IPC分类号： G06F11/26 , G06F11/36 , G06F11/34
CPC分类号： G06F11/261 , G06F11/3656
摘要： A micro processor emulator in which a set of core micro processor registers are the communication interface between an external system and a core-ported memory. The registers are connected to a serial scan port for transfer of information between a halted emulation environment and the external system. The serial port includes a command register that receives a jump address to initiate execution of a software monitor. Two special bits are provided in the command register, one that indicates a break, and one that indicates a Fast Break GO. This provides a break mechanism for a micro processor chip which does not have a dedicated memory bus. This break mechanism is the mechanism by which a halt or an asynchronous break is effected. After a fast break, the Fast Break GO mechanism does the action described by one command, and then immediately goes back to emulation without any external processor intervention.
摘要翻译：一种微处理器仿真器，其中一组核心微处理器寄存器是外部系统和核心端口存储器之间的通信接口。寄存器连接到串行扫描端口，用于在暂停的仿真环境和外部系统之间传输信息。串行端口包括一个命令寄存器，它接收跳转地址以启动软件监视器的执行。在命令寄存器中提供两个特殊位，一个表示一个中断，一个表示快速跳转GO。这为不具有专用存储器总线的微处理器芯片提供了中断机制。这种断开机制是实现停止或异步中断的机制。快速中断后，快速断点GO机制执行一个命令描述的动作，然后立即返回仿真，无需任何外部处理器干预。

8. 发明授权

US08661284B2 Method and system to improve the operations of a registered memory module 有权
标题翻译：改进注册内存模块操作的方法和系统
公开(公告)号：US08661284B2
公开(公告)日：2014-02-25
申请号：US13741532
申请日：2013-01-15
申请人： James W. Alexander , Kuljit S. Bains , Howard S. David
发明人： James W. Alexander , Kuljit S. Bains , Howard S. David
IPC分类号： G06F1/00 , G06F1/26 , G06F1/12 , G06F1/04 , G11C5/14 , G11C8/00 , G06F12/00
CPC分类号： G06F1/04 , G11C7/1045 , G11C7/1066 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a clock circuit in the registered memory module is being activated. In another embodiment of the invention, the registered memory module allows enabling or disabling of its clock circuit without any interruption of its operation. When the clock circuit in the registered memory module is disabled, the power consumption of the registered memory module can be reduced. In yet another embodiment of the invention, the registered memory module is allowed to enter or exit an asynchronous operation mode without entering or exiting a self-refresh or pre-charge power down operation mode of the registered memory module.
摘要翻译：一种改善注册内存模块操作的方法和系统。在本发明的一个实施例中，当登记的存储器模块中的时钟电路被激活时，所登记的存储器模块允许异步读取和写入操作。在本发明的另一个实施例中，登记的存储器模块允许其时钟电路的启用或禁用，而不会中断其操作。当注册的存储器模块中的时钟电路被禁用时，可以减少注册的存储器模块的功耗。在本发明的另一实施例中，允许登记的存储器模块进入或退出异步操作模式，而不进入或退出已注册存储器模块的自刷新或预充电掉电操作模式。

9. 发明申请

US20110320839A1 MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES 有权
标题翻译：通过动态内存操作状态进行存储电源管理
公开(公告)号：US20110320839A1
公开(公告)日：2011-12-29
申请号：US12821867
申请日：2010-06-23
申请人： Howard S. David , Ulf R. Hanebutte , Eugene Gorbatov , James W. Alexander , Suneeta Sah
发明人： Howard S. David , Ulf R. Hanebutte , Eugene Gorbatov , James W. Alexander , Suneeta Sah
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3275 , G06F1/3225 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/14 , Y02D10/172
摘要： Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory.
摘要翻译：这里描述了用于动态存储器频率/电压缩放以增加现有存储器功率管理技术并进一步提高存储器功率效率的技术。每个操作点被定义为存储器的操作状态。

10. 发明授权

US07516349B2 Synchronized memory channels with unidirectional links 有权
标题翻译：具有单向链路的同步存储信道
公开(公告)号：US07516349B2
公开(公告)日：2009-04-07
申请号：US11323345
申请日：2005-12-29
申请人： James W. Alexander , Rajat Agarwal , Pete D. Vogt
发明人： James W. Alexander , Rajat Agarwal , Pete D. Vogt
IPC分类号： G06F1/12 , G06F1/00 , G06F1/04
CPC分类号： G06F13/124
摘要： A memory agent may include a first memory channel interface and a second memory channel, both with unidirectional links, and logic to synchronize a signal processed by the first memory channel interface with a signal processed by the second memory channel interface. An embodiment of a method may include synchronizing a signal on a first memory channel with unidirectional links with a signal on a second memory channel with unidirectional links.
摘要翻译：存储器代理可以包括具有单向链路的第一存储器通道接口和第二存储器通道，以及用于将由第一存储器通道接口处理的信号与由第二存储器通道接口处理的信号同步的逻辑。一种方法的实施例可以包括使第一存储器通道上的信号与具有单向链路的第二存储器通道上的信号的单向链路同步。

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