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1. 发明授权

US06477769B2 Method for assembling a controlled impedance connector 失效
标题翻译：组装可控阻抗连接器的方法
公开(公告)号：US06477769B2
公开(公告)日：2002-11-12
申请号：US09780659
申请日：2001-02-09
申请人： Michael J. Lamatsch , Gerard A. Drewek , JoAnn M. Peterson
发明人： Michael J. Lamatsch , Gerard A. Drewek , JoAnn M. Peterson
IPC分类号： H01R4304
CPC分类号： H01R9/034 , H01R9/0512 , H01R9/0521 , Y10T29/49117 , Y10T29/49123 , Y10T29/49124 , Y10T29/49181
摘要： A method for assembling an impedance controlled connector using conventional connector shells and inserts and corresponding connector pins and sockets. Controlled impedance cables are prepared and physically arranged for termination in a conventional connector shell in a configuration which enhances the impedance control characteristic of the assembled connector. Assembly of the connector is effected using conventional materials and tools.
摘要翻译：一种使用常规连接器壳体和插入件以及相应的连接器引脚和插座组装阻抗控制连接器的方法。控制阻抗电缆被准备并物理地布置成用于以增强组装的连接器的阻抗控制特性的配置的常规连接器外壳中的端接。使用常规材料和工具来实现连接器的组装。

2. 发明授权

US06494743B1 Impedance-controlled connector 有权
标题翻译：阻抗控制连接器
公开(公告)号：US06494743B1
公开(公告)日：2002-12-17
申请号：US09607487
申请日：2000-06-30
申请人： Michael J. Lamatsch , Gerard A. Drewek
发明人： Michael J. Lamatsch , Gerard A. Drewek
IPC分类号： H01R13648
CPC分类号： H01R13/6586 , H01R13/6477
摘要： An electrical connector assembly using conventional signal pins is adapted for use with impedance-controlled cables by dividing the body of the connector into one or more separate channels. Each channel is defined by a perimeter providing electrical shielding. A separate impedance-controlled wire or cable can be terminated at conventional signal pins installed in an insert located within a particular channel. A transition region between a connector plug or receptacle and an incoming wire or cable preserves the correct impedance characteristics of the cable.
摘要翻译：使用常规信号引脚的电连接器组件适于与阻抗控制的电缆一起使用，其将连接器的主体分成一个或多个单独的通道。每个通道由提供电气屏蔽的周边限定。单独的阻抗控制的电线或电缆可以在安装在位于特定通道内的插入件中的常规信号引脚处终止。连接器插头或插座与输入的电线或电缆之间的过渡区域保留了电缆的正确阻抗特性。

3. 发明授权

US5627482A Electronic digital clock distribution system 失效
标题翻译：电子数字时钟分配系统
公开(公告)号：US5627482A
公开(公告)日：1997-05-06
申请号：US598233
申请日：1996-02-07
申请人： Michael J. Lamatsch
发明人： Michael J. Lamatsch
IPC分类号： G06F1/10 , H03K3/03 , H03K19/00
CPC分类号： H03K3/03 , G06F1/10
摘要： More particularly, an electronic digital clock distribution system provides a plurality of working rank clock signals to respective ones of a plurality of logic circuits. Each clock signal has a predetermined frequency and each logic circuit requires a working rank clock signal having a predetermined level of electrical power. An oscillator produces a master clock signal at the predetermined frequency and at an electrical power level at least equal to the sum of the power requirements for all working rank clock signals of the plurality of logic circuits. An electronic splitter network is connected to the oscillator to splitting the master clock signal into the plurality of working rank clock signals.
摘要翻译：更具体地，电子数字时钟分配系统向多个逻辑电路中的相应的一个逻辑电路提供多个工作秩时钟信号。每个时钟信号具有预定的频率，并且每个逻辑电路需要具有预定电力水平的工作秩时钟信号。振荡器以预定频率和至少等于多个逻辑电路的所有工作秩时钟信号的功率要求之和的电功率电平产生主时钟信号。电子分路器网络连接到振荡器以将主时钟信号分解成多个工作秩时钟信号。

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