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1. 发明申请

US20130299977A1 RAMP-STACK CHIP PACKAGE WITH VARIABLE CHIP SPACING 有权
标题翻译：具有可变芯片间隔的间歇式芯片包装
公开(公告)号：US20130299977A1
公开(公告)日：2013-11-14
申请号：US13468891
申请日：2012-05-10
申请人： Michael H. S. Dayringer , Nyles I. Nettleton , Robert David Hopkins, II
发明人： Michael H. S. Dayringer , Nyles I. Nettleton , Robert David Hopkins, II
IPC分类号： H01L23/498 , H01L23/488
CPC分类号： H01L25/0652 , H01L24/05 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81123 , H01L2224/81129 , H01L2225/06517 , H01L2225/06562 , H01L2225/06568 , H01L2225/06579 , H01L2924/00014 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.
摘要翻译：芯片封装包括彼此偏移的半导体管芯或芯片的堆叠，从而限定具有暴露焊盘的露台。此外，阶梯式台阶中的每个半导体管芯的表面包括大致平行于半导体管芯的边缘的两排第一焊盘。此外，芯片封装包括大致平行于平台的高带宽斜坡部件，并且具有包括布置在用于每个半导体管芯的至少两行第二焊盘中的第二焊盘的表面。第二焊盘通过连接器电连接和机械耦合到暴露的第一焊盘。因此，芯片封装中的电触点可以具有导电性，电容性或通常的复阻抗。此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。

2. 发明授权

US09082632B2 Ramp-stack chip package with variable chip spacing 有权
标题翻译：具有可变芯片间距的斜坡堆叠芯片封装
公开(公告)号：US09082632B2
公开(公告)日：2015-07-14
申请号：US13468891
申请日：2012-05-10
申请人： Michael H. S. Dayringer , Nyles I. Nettleton , Robert David Hopkins, II
发明人： Michael H. S. Dayringer , Nyles I. Nettleton , Robert David Hopkins, II
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L25/065 , H01L25/18 , H01L23/00
CPC分类号： H01L25/0652 , H01L24/05 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/73 , H01L24/81 , H01L25/0657 , H01L25/18 , H01L2224/0401 , H01L2224/0557 , H01L2224/1403 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/73203 , H01L2224/73253 , H01L2224/81123 , H01L2224/81129 , H01L2225/06517 , H01L2225/06562 , H01L2225/06568 , H01L2225/06579 , H01L2924/00014 , H01L2924/12042 , H01L2224/05552 , H01L2924/00
摘要： A chip package includes a stack of semiconductor dies or chips that are offset from each other, thereby defining a terrace with exposed pads. Moreover, surfaces of each of the semiconductor dies in the stepped terrace include two rows of first pads approximately parallel to edges of the semiconductor dies. Furthermore, the chip package includes a high-bandwidth ramp component, which is positioned approximately parallel to the terrace, and which has a surface that includes second pads arranged in at least two rows of second pads for each of the semiconductor dies. The second pads are electrically and mechanically coupled to the exposed first pads by connectors. Consequently, the electrical contacts in the chip package may have a conductive, a capacitive or, in general, a complex impedance. Furthermore, the chips and/or the ramp component may be positioned relative to each other using a ball-and-pit alignment technique.
摘要翻译：芯片封装包括彼此偏移的半导体管芯或芯片的堆叠，从而限定具有暴露焊盘的露台。此外，阶梯式台阶中的每个半导体管芯的表面包括大致平行于半导体管芯的边缘的两排第一焊盘。此外，芯片封装包括大致平行于平台的高带宽斜坡部件，并且具有包括布置在用于每个半导体管芯的至少两行第二焊盘中的第二焊盘的表面。第二焊盘通过连接器电连接和机械耦合到暴露的第一焊盘。因此，芯片封装中的电触点可以具有导电性，电容性或通常的复阻抗。此外，芯片和/或斜面部件可以使用球 - 坑对准技术相对于彼此定位。

3. 发明授权

US07425760B1 Multi-chip module structure with power delivery using flexible cables 有权
标题翻译：多芯片模块结构，采用柔性电缆供电
公开(公告)号：US07425760B1
公开(公告)日：2008-09-16
申请号：US11250100
申请日：2005-10-12
申请人： Bruce M. Guenin , Nyles I. Nettleton
发明人： Bruce M. Guenin , Nyles I. Nettleton
IPC分类号： H01L23/04 , H01L23/34
CPC分类号： H01L24/72 , H01L23/48 , H01L24/16 , H01L25/0652 , H01L25/0655 , H01L25/162 , H01L2224/16 , H01L2924/00011 , H01L2924/00014 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/14 , H01L2924/1532 , H01L2924/19104 , H01L2924/3011 , H01L2924/351 , H05K1/0263 , H05K1/147 , H01L2924/00 , H01L2224/0401
摘要： One embodiment of the present invention provides an integrated circuit module. This module includes a semiconductor die with an active face, upon which active circuitry and signal pads reside, and a back face opposite the active face. The module uses a flexible cable to deliver electrical power to the active face of the semiconductor die from a power distribution board located above the active face of the semiconductor die. This flexible cable provides electrical power to the semiconductor die without interfering with the alignment and heat removal functions of the module.
摘要翻译：本发明的一个实施例提供一种集成电路模块。该模块包括具有有源面的半导体管芯，有源电路和信号焊盘驻留在该半导体管芯上，以及与主动面相对的背面。该模块使用柔性电缆从位于半导体管芯的有源面上方的配电板向半导体管芯的有源面提供电力。该柔性电缆为半导体管芯提供电力，而不会干扰模块的对准和散热功能。

4. 发明申请

US20090002947A1 Evaporative cooling system for electronic components 审中-公开
标题翻译：电子元件蒸发冷却系统
公开(公告)号：US20090002947A1
公开(公告)日：2009-01-01
申请号：US12082640
申请日：2008-04-11
申请人： Nyles I. Nettleton , Howard L. Davidson
发明人： Nyles I. Nettleton , Howard L. Davidson
IPC分类号： H05K7/20
CPC分类号： H05K7/20336
摘要： An apparatus for cooling a number of electronic components comprises an enclosure within which the components are positioned, an arrangement for circulating a cooling fluid to the components so that the cooling fluid can evaporate on or proximate the components and thereby absorb the heat generated by the components, a mechanism for condensing the evaporated cooling fluid, and a reservoir which is in fluid communication with the circulating means and within which the condensed cooling fluid collects.
摘要翻译：用于冷却多个电子部件的装置包括其中定位有部件的外壳，用于将冷却流体循环到部件的布置，使得冷却流体可以在部件上或附近蒸发，从而吸收由部件产生的热量，用于冷凝蒸发的冷却流体的机构，以及与循环装置流体连通并且冷凝的冷却流体收集在其中的储存器。

5. 发明授权

US07372698B1 Electronics equipment heat exchanger system 有权
标题翻译：电子设备热交换器系统
公开(公告)号：US07372698B1
公开(公告)日：2008-05-13
申请号：US11614483
申请日：2006-12-21
申请人： Donald E. Tilton , Howard L. Davidson , Nyles I. Nettleton
发明人： Donald E. Tilton , Howard L. Davidson , Nyles I. Nettleton
IPC分类号： H05K7/00 , F28D15/00
CPC分类号： H05K7/20836 , H05K7/20772
摘要： An electronics equipment heat exchanger system for thermally managing the electronic devices of a computer server and the exhaust air emitted from the computer server. The electronics equipment heat exchanger system generally includes a heat exchanger attached near an air outlet of a support unit for a support rack, a thermal management unit fluidly connected to the heat exchanger, and a thermal conditioning unit fluidly connected to the thermal management unit and the heat exchanger. The thermal management unit directly thermally manages one or more electronic devices of the server mainboard while the heat exchanger thermally manages the exhaust air before the exhaust air exits through the outlet of the support unit of the computer server.
摘要翻译：一种用于热管理计算机服务器的电子设备和从计算机服务器发出的废气的电子设备热交换器系统。电子设备热交换器系统通常包括附接在用于支撑架的支撑单元的空气出口附近的热交换器，流体连接到热交换器的热管理单元和流体连接到热管理单元的热调节单元热交换器。热管理单元直接热管理服务器主板的一个或多个电子设备，而热交换器在排气通过计算机服务器的支撑单元的出口排出之前热管理废气。

6. 发明授权

US07043596B2 Method and apparatus for simulation processor 有权
公开(公告)号：US07043596B2
公开(公告)日：2006-05-09
申请号：US10113060
申请日：2002-03-29
申请人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
发明人： Thomas M. McWilliams , Jeffrey B. Rubin , Michael W. Parkin , Oyekunle A. Olukotun , Derek E. Pappas , Jeffrey M. Broughton , David R. Emberson , David S. Allison , Ashley N. Saulsbury , Earl T. Cohen , Nyles I. Nettleton , James B. Burr , Liang T. Chen
IPC分类号： G06F13/00 , H04L12/28
CPC分类号： G06F17/5022 , G06F15/8023 , H04L49/10 , H04L49/101
摘要： A method and apparatus for computation is provided. A main cluster crossbar is connected to a plurality of statically scheduled routing processors. A first sub-cluster crossbar is associated with a first one of the plurality of statically scheduled routing processors where the first sub-cluster crossbar is connected to a first plurality of execution processors. A second sub-cluster crossbar is associated with a second one of the plurality of statically scheduled routing processors where the second sub-cluster crossbar is connected to a second plurality of execution processors.

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