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1. 发明授权

US08482123B2 Stress reduction in chip packaging by using a low-temperature chip-package connection regime 有权
标题翻译：通过使用低温芯片封装连接方式降低芯片封装的压力
公开(公告)号：US08482123B2
公开(公告)日：2013-07-09
申请号：US13179643
申请日：2011-07-11
申请人： Michael Grillberger , Matthias Lehr , Thomas Werner
发明人： Michael Grillberger , Matthias Lehr , Thomas Werner
IPC分类号： H01L23/48
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05571 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/11825 , H01L2224/13007 , H01L2224/13011 , H01L2224/13012 , H01L2224/13014 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13186 , H01L2224/1319 , H01L2224/1357 , H01L2224/13644 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2224/17519 , H01L2224/81141 , H01L2224/81345 , H01L2224/81898 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.
摘要翻译：半导体芯片和封装基板可以通过在半导体芯片和封装基板中提供适当形状的互补的接触结构，在形式闭合的基础上直接连接。因此，可能不再需要焊料材料，因此可以避免组装过程中的任何升高的温度，这常常会导致显着的应力，从而造成损坏，特别是在非常复杂的金属化系统中。

2. 发明申请

US20120049350A1 Stress Reduction in Chip Packaging by Using a Low-Temperature Chip-Package Connection Regime 有权
标题翻译：使用低温芯片封装连接方式降低芯片封装的应力
公开(公告)号：US20120049350A1
公开(公告)日：2012-03-01
申请号：US13179643
申请日：2011-07-11
申请人： Michael Grillberger , Matthias Lehr , Thomas Werner
发明人： Michael Grillberger , Matthias Lehr , Thomas Werner
IPC分类号： H01L23/48 , H01L21/50 , H01L23/482
CPC分类号： H01L23/49811 , H01L21/4853 , H01L23/562 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L2224/0401 , H01L2224/05571 , H01L2224/11452 , H01L2224/11462 , H01L2224/11464 , H01L2224/11622 , H01L2224/11825 , H01L2224/13007 , H01L2224/13011 , H01L2224/13012 , H01L2224/13014 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13186 , H01L2224/1319 , H01L2224/1357 , H01L2224/13644 , H01L2224/14051 , H01L2224/16225 , H01L2224/16227 , H01L2224/17517 , H01L2224/17519 , H01L2224/81141 , H01L2224/81345 , H01L2224/81898 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor chip and a package substrate may be directly connected on the basis of form closure by providing appropriately shaped complementary contact structures in the semiconductor chip and the package substrate. Consequently, solder material may no longer be required and thus any elevated temperatures during the assembly process may be avoided, which may conventionally result in significant stress forces, thereby creating damage, in particular in very complex metallization systems.
摘要翻译：半导体芯片和封装基板可以通过在半导体芯片和封装基板中提供适当形状的互补的接触结构，在形式闭合的基础上直接连接。因此，可能不再需要焊料材料，因此可以避免组装过程中的任何升高的温度，这常常会导致显着的应力，从而造成损坏，特别是在非常复杂的金属化系统中。

3. 发明申请

US20090243116A1 REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS 有权
标题翻译：通过降低TRENCH电介质的污染，降低金属化层堆叠中的铁素体与低K材料的可变性
公开(公告)号：US20090243116A1
公开(公告)日：2009-10-01
申请号：US12355112
申请日：2009-01-16
申请人： Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
发明人： Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76808 , H01L21/76831 , H01L21/76835 , H01L23/5226 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.
摘要翻译：通过在用于首先图形化通孔和沟槽的双镶嵌策略期间施加平坦化层之前形成保护层，可以实现增强的蚀刻保真度。在本文公开的其他方面，通孔开口和沟槽可以在单独的步骤中被图案化，其可以通过各个介电材料的不同蚀刻行为和/或提供适当的蚀刻停止层来实现，同时将通孔开口和沟槽填充可以在共同的填充序列中实现阻挡材料和高导电性金属。因此，可以基于减小的纵横比来形成通孔开口，同时提供高效的总体工艺顺序。

4. 发明授权

US08357610B2 Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics 有权
标题翻译：通过减少沟槽电介质的污染，减少具有低k材料的金属化层堆叠中的沟槽的图案变化
公开(公告)号：US08357610B2
公开(公告)日：2013-01-22
申请号：US12355112
申请日：2009-01-16
申请人： Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
发明人： Frank Feustel , Thomas Werner , Michael Grillberger , Kai Frohberg
IPC分类号： H01L21/308 , H01L21/768
CPC分类号： H01L21/76877 , H01L21/76807 , H01L21/76808 , H01L21/76831 , H01L21/76835 , H01L23/5226 , H01L23/53238 , H01L23/53252 , H01L23/5329 , H01L23/53295 , H01L2221/1031 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.
摘要翻译：通过在用于首先图形化通孔和沟槽的双镶嵌策略期间施加平坦化层之前形成保护层，可以实现增强的蚀刻保真度。在本文公开的其他方面，通孔开口和沟槽可以在单独的步骤中被图案化，其可以通过各个介电材料的不同蚀刻行为和/或提供适当的蚀刻停止层来实现，同时将通孔开口和沟槽填充可以在共同的填充序列中实现阻挡材料和高导电性金属。因此，可以基于减小的纵横比来形成通孔开口，同时提供高效的总体工艺顺序。

5. 发明授权

US09318468B2 3-D integrated semiconductor device comprising intermediate heat spreading capabilities 有权
标题翻译：包括中间散热能力的3-D集成半导体器件
公开(公告)号：US09318468B2
公开(公告)日：2016-04-19
申请号：US13300913
申请日：2011-11-21
申请人： Thomas Werner , Michael Grillberger , Frank Feustel
发明人： Thomas Werner , Michael Grillberger , Frank Feustel
IPC分类号： H01L23/34 , H01L25/065
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06589 , H01L2924/1305 , H01L2924/00 , H01L2924/00014
摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
摘要翻译：在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

6. 发明申请

US20120061818A1 3-D Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilites 审中-公开
标题翻译：包括中间热传递能力的3-D集成半导体器件
公开(公告)号：US20120061818A1
公开(公告)日：2012-03-15
申请号：US13300913
申请日：2011-11-21
申请人： Thomas Werner , Michael Grillberger , Frank Feustel
发明人： Thomas Werner , Michael Grillberger , Frank Feustel
IPC分类号： H01L23/34
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06589 , H01L2924/1305 , H01L2924/00 , H01L2924/00014
摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
摘要翻译：在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

7. 发明授权

US08080866B2 3-D integrated semiconductor device comprising intermediate heat spreading capabilities 有权
标题翻译：包括中间散热能力的3-D集成半导体器件
公开(公告)号：US08080866B2
公开(公告)日：2011-12-20
申请号：US12506536
申请日：2009-07-21
申请人： Thomas Werner , Michael Grillberger , Frank Feustel
发明人： Thomas Werner , Michael Grillberger , Frank Feustel
IPC分类号： H01L23/52
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06589 , H01L2924/1305 , H01L2924/00 , H01L2924/00014
摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
摘要翻译：在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

8. 发明申请

US20100052134A1 3-D INTEGRATED SEMICONDUCTOR DEVICE COMPRISING INTERMEDIATE HEAT SPREADING CAPABILITIES 有权
标题翻译：包含中间热传递能力的3-D集成半导体器件
公开(公告)号：US20100052134A1
公开(公告)日：2010-03-04
申请号：US12506536
申请日：2009-07-21
申请人： Thomas Werner , Michael Grillberger , Frank Feustel
发明人： Thomas Werner , Michael Grillberger , Frank Feustel
IPC分类号： H01L23/52 , H01L21/50 , H01L21/58 , H01L23/373
CPC分类号： H01L25/0657 , H01L25/50 , H01L2224/05001 , H01L2224/05022 , H01L2224/051 , H01L2224/05572 , H01L2224/056 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06589 , H01L2924/1305 , H01L2924/00 , H01L2924/00014
摘要： In a three-dimensional chip configuration, a heat spreading material may be positioned between adjacent chips and also between a chip and a carrier substrate, thereby significantly enhancing heat dissipation capability. Furthermore, appropriately sized and positioned through holes in the heat spreading material may enable electrical chip-to-chip connections, while responding thermally conductive connectors may extend to the heat sink without actually contacting the corresponding chips.
摘要翻译：在三维芯片构造中，散热材料可以位于相邻的芯片之间以及芯片和载体衬底之间，从而显着提高散热能力。此外，通过散热材料中的孔的适当尺寸和定位可以实现电芯片到芯片的连接，而响应的导热连接器可以延伸到散热器而不实际接触相应的芯片。

9. 发明授权

US09822377B2 Mutant CD83 promoter and use thereof 有权
公开(公告)号：US09822377B2
公开(公告)日：2017-11-21
申请号：US14113844
申请日：2012-04-27
申请人： Alexander Steinkasserer , Marcello Stein , Thomas Werner , Ilka Knippertz
发明人： Alexander Steinkasserer , Marcello Stein , Thomas Werner , Ilka Knippertz
IPC分类号： C12N15/85 , C12N15/86
CPC分类号： C12N15/85 , C12N15/86 , C12N2710/10041
摘要： The present invention provides a mutant CD83 promoter comprising the promoter/enhancer regions of human CD83 promoter and being dendritic cell-specific, and the use thereof, specifically for the treatment or prevention of diseases or medical conditions related to malignancy, autoimmunity or prevention of transplant rejections.

10. 发明授权

US09272732B2 Method for determining a rack force for a steering apparatus and steering apparatus 有权
标题翻译：用于确定转向装置和转向装置的齿条力的方法
公开(公告)号：US09272732B2
公开(公告)日：2016-03-01
申请号：US14347822
申请日：2012-09-10
申请人： Roland Greul , Thomas Werner , Joerg Strecker
发明人： Roland Greul , Thomas Werner , Joerg Strecker
IPC分类号： B62D15/02 , B62D6/00
CPC分类号： B62D15/0225 , B62D6/008
摘要： A method for determining a rack force for a steering apparatus of a vehicle, in which the rack force is determined as a function of a steering angle variable which characterizes an actual wheel steering angle or a set point of the wheel steering angle. In order to specify a method for determining a rack force, with which a target steering torque can be generated such that a comfortable steering feel is imparted to the driver and the steering apparatus nevertheless gives the driver feedback that is as realistic as possible regarding the motion state of the vehicle, the method comprises: determining a variable which characterizes a lateral force on a shaft of the steering apparatus, and determining the rack force as a function of the lateral force, wherein the determination of the rack force comprises a filtering by means of a signal processing element having a proportional-differential transfer function.
摘要翻译：一种用于确定车辆转向装置的齿条力的方法，其中机架力被确定为表征车轮转向角的实际车轮转向角或设定点的转向角变量的函数。为了确定用于确定机架力的方法，通过该方法可以产生目标转向扭矩，使得向驾驶员和转向装置赋予舒适的转向感，然而给予驾驶员对于运动尽可能现实的反馈该方法包括：确定表征转向装置的轴上的横向力的变量，以及确定作为横向力的函数的齿条力，其中机架力的确定包括通过装置的过滤具有比例差分传递函数的信号处理元件。

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