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1. 发明授权

US06650323B2 Graphics system having a super-sampled sample buffer and having single sample per pixel support 有权
标题翻译：图形系统具有超采样采样缓冲器并且每像素支持单个采样
公开(公告)号：US06650323B2
公开(公告)日：2003-11-18
申请号：US10194976
申请日：2002-07-12
申请人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
发明人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
IPC分类号： G06T1500
CPC分类号： G09G5/391 , G06T15/503 , G09G5/14 , G09G5/363 , G09G5/397 , G09G2340/0407 , G09G2354/00 , G09G2360/10 , G09G2360/121
摘要： A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer and may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. The graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to provide backwards compatibility with legacy systems.
摘要翻译：利用超采样采样缓冲器和用于刷新显示器的采样到像素计算单元的计算机图形系统。图形系统可以具有图形处理器，超采样采样缓冲器和采样到像素的计算单元。图形处理器将样本呈现到样本缓冲器中，并且可以利用在每个对象的基础上指定像素的属性的窗口ID。窗口ID可以指定样本模式，过滤器类型，颜色属性或源属性中的一个或多个。样本模式可以包括每像素模式的单个样本和每像素模式的多个采样。图形系统可以进一步可操作以为屏幕的某些窗口生成每个像素的单个样本，以便向遗留系统提供向后兼容性。

2. 发明授权

US06982719B2 Switching sample buffer context in response to sample requests for real-time sample filtering and video generation 有权
标题翻译：响应样本请求进行实时样本过滤和视频生成，切换采样缓冲区上下文
公开(公告)号：US06982719B2
公开(公告)日：2006-01-03
申请号：US10195827
申请日：2002-07-15
申请人： Michael F. Deering , Nathaniel David Naegle , Michael G. Lavelle
发明人： Michael F. Deering , Nathaniel David Naegle , Michael G. Lavelle
IPC分类号： G09G5/399
CPC分类号： G06T15/005 , G09G5/363
摘要： A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to generate samples in response to received graphics data, and to forward the samples to the scheduling network for storage in the sample buffer. The filtering engine is configured to send a request for samples to the scheduling network. The scheduling network is configured to compare a video set designation of the request to a previous request designation, to update one or more state registers in one or more memory devices of the sample buffer in response to a determination that the video set designation of the request is different from the previous request designation, and to assert signals inducing a transfer of a collection of samples corresponding to the request from the one or more memory devices to the filtering engine.
摘要翻译：配置有调度网络，采样缓冲器，呈现引擎和过滤引擎的图形系统。渲染引擎被配置为响应于接收到的图形数据生成样本，并且将样本转发到调度网络以存储在采样缓冲器中。过滤引擎被配置为向调度网络发送样本请求。调度网络被配置为将请求的视频集指定与先前的请求指定进行比较，以响应于确定该请求的视频集指定，来更新采样缓冲器的一个或多个存储器设备中的一个或多个状态寄存器与先前的请求指定不同，并且声明诱导将来自一个或多个存储器设备的对应于请求的样本集合传送到过滤引擎的信号。

3. 发明授权

US06753870B2 Graphics system configured to switch between multiple sample buffer contexts 有权
标题翻译：图形系统配置为在多个样本缓冲区上下文之间切换
公开(公告)号：US06753870B2
公开(公告)日：2004-06-22
申请号：US10060968
申请日：2002-01-30
申请人： Michael F. Deering , Nathaniel David Naegle , Michael G. Lavelle
发明人： Michael F. Deering , Nathaniel David Naegle , Michael G. Lavelle
IPC分类号： G09G539
CPC分类号： G09G5/393 , G09G5/391 , G09G5/42
摘要： A graphics system comprising a programmable sample buffer and a sample buffer interface. The sample buffer interface is configured to (a) buffer N streams of samples in N corresponding input buffers, wherein N is greater than or equal to two, (b) store N sets of context values corresponding to the N input buffers respectively, (c) terminate transfer of samples from a first of the input buffers to the programmable sample buffer, (d) selectively update a subset of state registers in the programmable sample buffer with context values corresponding to a next input buffer of the input buffers, (e) initiate transfer of samples from the next input buffer to the programmable sample buffer. The context values stored in the state registers of the programmable sample buffer determine the operation of an arithmetic logic unit internal to the programmable sample buffer on samples data.
摘要翻译：包括可编程样本缓冲器和样本缓冲器接口的图形系统。样本缓冲器接口被配置为（a）在N个对应的输入缓冲器中缓冲N个采样流，其中N大于或等于2，（b）分别存储与N个输入缓冲器对应的N组上下文值，（c （d）选择性地更新可编程样本缓冲器中的状态寄存器的子集，其中上下文值对应于输入缓冲器的下一个输入缓冲器，（e）可选择性地更新可编程采样缓冲器中的第一个输入缓冲器的样本，启动样品从下一个输入缓冲器传输到可编程样品缓冲液。存储在可编程样本缓冲器的状态寄存器中的上下文值确定可编程样本缓冲器内部的算术逻辑单元对样本数据的操作。

4. 发明授权

US06496187B1 Graphics system configured to perform parallel sample to pixel calculation 有权
标题翻译：图形系统配置为执行并行采样到像素计算
公开(公告)号：US06496187B1
公开(公告)日：2002-12-17
申请号：US09472940
申请日：1999-12-27
申请人： Michael F. Deering , Nathaniel David Naegle , Scott R. Nelson
发明人： Michael F. Deering , Nathaniel David Naegle , Scott R. Nelson
IPC分类号： G06T1500
CPC分类号： G06T5/20 , G06T11/001 , G06T11/40 , G06T15/503
摘要： A graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. The graphics system may include a graphics processor, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processor is configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer is configured to store the plurality of samples for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical or horizontal stripe of the image, or a rectangular portion of the image. Each region may overlap the other regions of the image to prevent visual aberrations.
摘要翻译：被配置为利用采样缓冲器和多个平行的样本到像素计算单元的图形系统，其中采样像素计算单元被配置为并行地访问样本缓冲器的不同部分。图形系统可以包括图形处理器，采样缓冲器和多个采样到像素的计算单元。图形处理器被配置为接收一组三维图形数据并且基于图形数据呈现多个采样。样本缓冲器被配置为存储用于样本到像素计算单元的多个样本，其被配置为从样本缓冲器接收和过滤样本以创建输出像素。每个样本到像素计算单元被配置为生成与图像的不同区域相对应的像素。该区域可以是图像的垂直或水平条纹，或图像的矩形部分。每个区域可能与图像的其他区域重叠以防止视觉异常。

5. 发明授权

US06816162B2 Data management to enable video rate anti-aliasing convolution 有权
标题翻译：数据管理使视频速率反锯齿卷积
公开(公告)号：US06816162B2
公开(公告)日：2004-11-09
申请号：US10200087
申请日：2002-07-19
申请人： Nimita J. Taneja , Nathaniel David Naegle , Michael F. Deering
发明人： Nimita J. Taneja , Nathaniel David Naegle , Michael F. Deering
IPC分类号： G06F1300
CPC分类号： G06T11/40 , G06T5/20
摘要： A system and method is disclosed for management of sample data to enable video rate anti-aliasing convolution. Sample data may be moved simultaneously from a sample buffer to a bin scanline cache and from the bin scanline cache to an array of N2 processor—memory units (e.g. 25 for N=5). Pixel data may be convolved from an N×N sample bin array that may be approximately centered on the pixel location. Since each sample bin contains Ns/b samples, Ns/b×N2 samples may be filtered for each pixel (e.g. 400 for N=5 and Ns/b=16). Each processor—memory unit convolves the sample data for one sample bin in the N×N sample bin array and supports a variety of filter functions. Pixel data may be output to a real time video data stream.
摘要翻译：公开了一种用于管理样本数据以实现视频速率抗混叠卷积的系统和方法。样本数据可以同时从采样缓冲器移动到bin扫描线高速缓存，并且从bin扫描线高速缓存移动到N 2个处理器存储器单元的阵列（例如，对于N = 5为25）。像素数据可以从可以近似于像素位置的中心的N×N样本仓阵列卷积。由于每个样本箱包含Ns / b个样本，因此可以针对每个像素滤波Ns / bxN <2个样本（例如N = 5和Ns / b = 16的400）。每个处理器存储器单元将一个样本仓的样本数据卷积在NxN样本仓阵列中，并支持各种滤波器功能。像素数据可以输出到实时视频数据流。

6. 发明授权

US06795076B2 Graphics system with real-time convolved pixel readback 有权
标题翻译：具有实时卷积像素回读的图形系统
公开(公告)号：US06795076B2
公开(公告)日：2004-09-21
申请号：US09894068
申请日：2001-06-28
申请人： Michael F. Deering , Nathaniel David Naegle
发明人： Michael F. Deering , Nathaniel David Naegle
IPC分类号： G06F1516
CPC分类号： G06T1/20 , G06F3/14 , G06T15/005
摘要： A graphics system comprising a control unit and a series of calculation units coupled together in a closed chain by a segmented communication bus. The calculation unit collaboratively generate one or more video signals. Each calculation unit is programmably assigned to contribute its locally-generated pixels to one of the video streams. The control unit sends a frame readback request to a selected one of the calculation units through the segmented communication bus. The frame readback request specifies some subset of the pixels in one of the video streams for readback to the control unit. In response to the frame readback request, the selected calculation unit transmits the subset of pixels of the specified video stream to the control unit, and the control unit forwards the subset of pixels to a target memory block (e.g. in system memory of a host computer or memory within the graphics system).
摘要翻译：一种图形系统，包括控制单元和通过分段通信总线在闭合链中耦合在一起的一系列计算单元。计算单元协同生成一个或多个视频信号。可编程地分配每个计算单元以将其本地生成的像素贡献给一个视频流。控制单元通过分段通信总线向所选择的一个计算单元发送帧回读请求。帧回读请求指定一个视频流中的像素的一些子集，用于回读到控制单元。响应于帧回读请求，所选择的计算单元将指定的视频流的像素的子集发送到控制单元，并且控制单元将像素子集转发到目标存储器块（例如，在主计算机的系统存储器中）或图形系统内的内存）。

7. 发明授权

US06885384B2 Method of creating a larger 2-D sample location pattern from a smaller one by means of X, Y address permutation 有权
标题翻译：通过X，Y地址排列从较小的2-D样本位置模式创建较大的2-D样本位置模式的方法
公开(公告)号：US06885384B2
公开(公告)日：2005-04-26
申请号：US10387357
申请日：2003-03-12
申请人： Michael F. Deering , Nathaniel David Naegle , Ranjit S. Oberoi
发明人： Michael F. Deering , Nathaniel David Naegle , Ranjit S. Oberoi
IPC分类号： G06F12/02 , G06T11/40 , G06T15/00 , G06T15/50 , G09G5/00
CPC分类号： G06T15/50 , G06T11/40 , G06T15/005
摘要： A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This method, for example, allows hardware to effectively reproduce a pre-selected set of sample locations for an array of 128×128 sample bins from a smaller set of pre-selected sample locations for an array of 2×2 sample bins. A permutation logic unit may use a first portion of an address for a sample bin B to identify a corresponding 2-D transformation, apply the inverse of the transformation to a second portion of the sample bin address to identify the corresponding bin of the 2×2 array of sample bins, and apply the transformation to the sample locations stored in the corresponding bin to reproduce the sample locations pre-selected for sample bin B.
摘要翻译：公开的系统和方法用于通过X，Y地址排列从较小的2-D采样位置模式再现预选的较大的2-D采样位置模式。例如，该方法允许硬件有效地再现来自用于2×2个样本仓阵列的较小的一组预先选择的样本位置的128×128个样本仓阵列的预先选定的样本位置集合。置换逻辑单元可以使用用于样本箱B的地址的第一部分来识别对应的2-D变换，将变换的反向应用于样本仓地址的第二部分以识别2x2阵列的相应仓的样品箱，并将变换应用于存储在相应仓中的样品位置，以再现样品箱B预先选择的样品位置。

8. 发明授权

US06417861B1 Graphics system with programmable sample positions 有权
标题翻译：具有可编程样品位置的图形系统
公开(公告)号：US06417861B1
公开(公告)日：2002-07-09
申请号：US09251449
申请日：1999-02-17
申请人： Michael F. Deering , Nathaniel David Naegle , Scott Nelson
发明人： Michael F. Deering , Nathaniel David Naegle , Scott Nelson
IPC分类号： G09G502
CPC分类号： G06T15/005
摘要： A method and computer graphics system for rendering images using programmable sample positions is disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples using a sample positioning algorithm selected from a programmable memory or generated by programmable hardware. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample buffer may be super-sampled and double buffered. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types. The algorithms used to position the samples may position the samples according to a regular grid, a perturbed regular grid, or a stochastic grid.
摘要翻译：公开了一种使用可编程样本位置渲染图像的方法和计算机图形系统。在一个实施例中，计算机图形系统可以包括图形处理器，采样缓冲器和采样到像素的计算单元。图形处理器可以被配置为使用从可编程存储器中选择的或由可编程硬件产生的样本定位算法来生成多个采样。耦合到图形处理器的采样缓冲器可以被配置为存储样本。采样缓冲器可以是超采样和双重缓冲。样本到像素计算单元是可编程的，以从样本缓冲器中选择可变数量的存储样本以过滤到输出像素中。采样到像素计算单元实时执行滤波处理，可以使用多种不同的滤波器类型。用于定位样本的算法可以根据规则网格，扰动的规则网格或随机网格来定位样本。

9. 发明授权

US08593468B2 Scalable high performance 3D graphics 有权
标题翻译：可扩展的高性能3D图形
公开(公告)号：US08593468B2
公开(公告)日：2013-11-26
申请号：US12898249
申请日：2010-10-05
申请人： Michael F. Deering , Michael G. Lavelle
发明人： Michael F. Deering , Michael G. Lavelle
IPC分类号： G06F13/14 , G06F12/02 , G06T1/20
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译：高速环形拓扑。在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。

10. 发明申请

US20110221742A1 Scalable High Performance 3D Graphics 有权
标题翻译：可扩展的高性能3D图形
公开(公告)号：US20110221742A1
公开(公告)日：2011-09-15
申请号：US12898249
申请日：2010-10-05
申请人： Michael F. Deering , Michael G. Lavelle
发明人： Michael F. Deering , Michael G. Lavelle
IPC分类号： G06T15/00
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译：高速环形拓扑。在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。

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