专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5870332A High reliability logic circuit for radiation environment 失效
标题翻译：用于辐射环境的高可靠性逻辑电路
公开(公告)号：US5870332A
公开(公告)日：1999-02-09
申请号：US635794
申请日：1996-04-22
申请人： Michael D. Lahey , Debra S. Harris , Harry N. Gardner , Michael J. Barry
发明人： Michael D. Lahey , Debra S. Harris , Harry N. Gardner , Michael J. Barry
IPC分类号： H03K19/20 , G11C5/00 , H03K3/037 , G11C11/40
CPC分类号： H03K3/0375 , G11C5/005
摘要： A high reliability logic circuit designed to withstand a single event upset (SEU) induced by an ion transitioning through a semiconductor structure is embodied in a memory circuit which includes a first memory cell and a second memory cell. The first and second memory cells receive a first input signal and a second input signal. The memory cells contain a logic circuit for producing a logic signal output driven by either a pullup or pulldown driver when the first and second input signals are of a desired logic state and produces a high impedance output if either input signal is not of their respective desired logic states.The memory cells also have sufficient nodal capacitance such that the output from the first or second memory cell will not be corrupted by an SEU in the logic circuit of either the first or second memory cell.The outputs of the first memory cell and second memory cell are further summed in analog fashion to produce a single output from the memory circuit. The summing of the output signals from the first and second memory cell prevents a single error in either memory cell from propagating to a next stage.
摘要翻译：设计成承受由通过半导体结构转移的离子引起的单个事件不正常（SEU）的高可靠性逻辑电路体现在包括第一存储单元和第二存储单元的存储器电路中。第一和第二存储单元接收第一输入信号和第二输入信号。当第一和第二输入信号是期望的逻辑状态时，存储器单元包含用于产生由上拉驱动器或下拉驱动器驱动的逻辑信号输出的逻辑电路，并且如果任一输入信号不是它们各自期望的，则产生高阻抗输出逻辑状态。存储单元也具有足够的节点电容，使得来自第一或第二存储单元的输出不会被第一或第二存储单元的逻辑电路中的SEU所破坏。第一存储器单元和第二存储器单元的输出进一步以模拟方式相加以产生来自存储器电路的单个输出。来自第一和第二存储器单元的输出信号的相加防止任一存储器单元中的单个错误传播到下一级。

2. 发明授权

US06453447B1 Method for fabricating integrated circuits 有权
标题翻译：集成电路制造方法
公开(公告)号：US06453447B1
公开(公告)日：2002-09-17
申请号：US09640344
申请日：2000-08-16
申请人： Harry N. Gardner , Debra S. Harris , Michael D. Lahey , Stacia L. Patton , Peter M. Pohlenz
发明人： Harry N. Gardner , Debra S. Harris , Michael D. Lahey , Stacia L. Patton , Peter M. Pohlenz
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.
摘要翻译：逻辑电路的功能和几何子组件在集成电路的设计中被定义和使用，以促进用于具有不同设计规则的铸造厂的集成电路设计的转换。

3. 发明授权

US06346427B1 Parameter adjustment in a MOS integrated circuit 有权
标题翻译： MOS集成电路中的参数调整
公开(公告)号：US06346427B1
公开(公告)日：2002-02-12
申请号：US09376246
申请日：1999-08-18
申请人： Harry N. Gardner , Debra S. Harris , Michael D. Lahey , Stacia L. Patton , Peter M. Pohlenz
发明人： Harry N. Gardner , Debra S. Harris , Michael D. Lahey , Stacia L. Patton , Peter M. Pohlenz
IPC分类号： H01L2100
CPC分类号： H01L22/20 , H01L29/0692 , H01L29/4238
摘要： A method of manufacturing an integrated circuit including adjusting a parameter of the operation of the integrated circuit, such as power dissipation, after prototype testing by changing only one mask. If prototype testing indicates that the performance specification for power dissipation, for example, is not met, the power dissipation can be adjusted by changing the size of the active areas to change the channel width of the gates of the circuit, by changing the size of the patterns of the active area masks. To decrease power dissipation, the size of the active area is decreased. Only the active mask need be changed. Preferably, the active area around the original contacts are maintained so that the positions of the contacts need not be changed. Consequently, the mask for defining the position of the contacts and the masks for defining the metallization layers need not be changed. To increase power dissipation, the size of the active areas is increased. The values of other parameters may be changed, as well.
摘要翻译：一种制造集成电路的方法，包括通过仅改变一个掩模，在原型测试之后调整诸如功率消耗的集成电路的操作参数。如果原型测试表明功率耗散的性能规格不符合要求，可以通过改变有源区域的尺寸来改变功率损耗，从而改变电路的栅极的通道宽度，活动区域掩模的图案。为了降低功耗，有效区域的尺寸减小。只有主动面罩需要改变。优选地，保持原始触点周围的有源区域，使得触点的位置不需要改变。因此，用于限定触点的位置的掩模和用于限定金属化层的掩模不需要改变。为了增加功耗，有效区域的大小增加。其他参数的值也可以改变。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式