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1. 发明授权

US5430398A BiCMOS buffer circuit 失效
标题翻译： BiCMOS缓冲电路
公开(公告)号：US5430398A
公开(公告)日：1995-07-04
申请号：US176558
申请日：1994-01-03
申请人： Michael D. Cooper , Robert C. Martin , Stanley C. Keeney
发明人： Michael D. Cooper , Robert C. Martin , Stanley C. Keeney
IPC分类号： H03K19/0944 , H03K19/20
CPC分类号： H03K19/09448
摘要： A BiCMOS non-inverting buffer circuit (40) with small fan-in capacitance and excellent bipolar output drive. The circuit is ideal for buffering CMOS logic gates from excessive fan-out loads. The circuit also is less complex and more silicon efficient than present buffer circuit implementations, it provides improved transient saturation charge clamping and one buffer macro in an ASIC library can provide extended drive capability to all CMOS logic gates in the library.
摘要翻译：一个BiCMOS非反相缓冲电路（40），具有小的扇入电容和出色的双极性输出驱动。该电路非常适合缓冲CMOS逻辑门从过多的扇出负载。该电路与现在的缓冲电路实现相比并不复杂，硅效率更高，它提供了改进的瞬态饱和电荷钳位，ASIC库中的一个缓冲器宏可以为库中的所有CMOS逻辑门提供扩展的驱动能力。

2. 发明授权

US5844954A Fine resolution digital delay line with coarse and fine adjustment stages 失效
公开(公告)号：US5844954A
公开(公告)日：1998-12-01
申请号：US802498
申请日：1997-02-20
申请人： Joseph A. Casasanta , Bernhard H. Andresen , Yoshinori Satoh , Stanley C. Keeney , Robert C. Martin
发明人： Joseph A. Casasanta , Bernhard H. Andresen , Yoshinori Satoh , Stanley C. Keeney , Robert C. Martin
IPC分类号： G06F1/10 , H03K5/13 , H03L7/081 , H03D3/24
CPC分类号： H03K5/133 , G06F1/10 , H03K5/131 , H03L7/0812 , H03L7/0814
摘要： A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.

3. 发明授权

US5355037A High performance digital phase locked loop 失效
标题翻译：高性能数字锁相环
公开(公告)号：US5355037A
公开(公告)日：1994-10-11
申请号：US898981
申请日：1992-06-15
申请人： Bernhard H. Andresen , Joseph A. Casasanta , Stanley C. Keeney , Robert C. Martin , Yoshinori Satoh
发明人： Bernhard H. Andresen , Joseph A. Casasanta , Stanley C. Keeney , Robert C. Martin , Yoshinori Satoh
IPC分类号： H03K5/00 , G06F1/10 , G06F1/12 , G11C11/407 , H03K5/13 , H03K5/135 , H03L7/081 , H03L7/085 , H03K17/28
CPC分类号： H03K5/135 , G06F1/10 , H03K5/131 , H03L7/0814 , H03L7/085
摘要： A first periodic digital waveform is to be synchronized with a second periodic digital waveform obtained by propagating the first waveform through a delay path (13) having an adjustable propagation delay. In the disclosed approach, the delay of the delay path is increased, even when an edge (43) of the second waveform trails a corresponding edge (45) of the first waveform by less than one-half cycle. The delay continues to be increased until the edge of the second waveform is eventually time-shifted past the next successive corresponding edge (49) of the first waveform.
摘要翻译：第一周期数字波形将与通过传播具有可调传播延迟的延迟路径（13）传播第一波形而获得的第二周期数字波形同步。在所公开的方法中，延迟路径的延迟增加，即使当第二波形的边缘（43）将第一波形的相应边缘（45）跟踪小于半个周期时。延迟继续增加，直到第二波形的边缘最终经过第一波形的下一个相继的相应边缘（49）时间偏移。

4. 发明授权

US5153457A Output buffer with DI/DT and DV/DT and Tri-State Control 失效
标题翻译：具有DI / DT和DV / DT和三态控制的输出缓冲器
公开(公告)号：US5153457A
公开(公告)日：1992-10-06
申请号：US626160
申请日：1990-12-12
申请人： Robert C. Martin , Stanley C. Keeney
发明人： Robert C. Martin , Stanley C. Keeney
IPC分类号： H03F1/52 , G11C7/10 , H03K19/003 , H03K19/0175
CPC分类号： H03K19/00361 , G11C7/1051
摘要： An output buffer (12) is provided for producing an output signal varying between a voltage on a first lien (22) and a voltage on a second line (36). First output circuitry (3, 4) is provided for pulling an output terminal (26) to the voltage on first line (22). Second output circuitry (6, 7) is provided for pulling output terminal (26) to the voltage on second line (36) in response to an input thereto. First feedback circuitry (2, 8) is provided for detecting a voltage spike on first line (22) and varying the input to first output circuitry (3 4) in response. Second feedback circuitry (5, 9) is provided for detecting a voltage spike on second line (36) and varying the input to second output circuitry (6, 7) in response.

5. 发明授权

US5544203A Fine resolution digital delay line with coarse and fine adjustment stages 失效
标题翻译：精细分辨率数字延迟线，粗调和微调阶段
公开(公告)号：US5544203A
公开(公告)日：1996-08-06
申请号：US324856
申请日：1994-10-18
申请人： Joseph A. Casasanta , Bernhard H. Andresen , Yoshinori Satoh , Stanley C. Keeney , Robert C. Martin
发明人： Joseph A. Casasanta , Bernhard H. Andresen , Yoshinori Satoh , Stanley C. Keeney , Robert C. Martin
IPC分类号： G06F1/10 , H03K5/13 , H03L7/081 , H03D3/24
CPC分类号： H03K5/133 , G06F1/10 , H03K5/131 , H03L7/0812 , H03L7/0814
摘要： A device and method for reducing phase jitter in digital phase locked loop applications resulting in smaller clock skews between application specific integrated circuits (ASICs). Phase jitter is reduced by a fine resolution digital delay line (20) comprising both coarse stages (variable delay element 24) for rough/fast phase adjustment and fine stages (fine resolution delay element 22) for precise delay adjustment when phase lock is near.
摘要翻译：用于减少数字锁相环应用中的相位抖动的装置和方法，导致专用集成电路（ASIC）之间的较小的时钟偏差。通过精细分辨率数字延迟线（20）减少相位抖动，该精细分辨率数字延迟线（20）包括用于粗略/快速相位调整的粗略级（可变延迟元件24）和当相位锁定时精确延迟调整的精细级（精细分辨率延迟元件22）。

6. 发明授权

US5532616A On-chip series terminated CMOS(Bi-CMOS) driver 失效
标题翻译：片上系列端接CMOS（Bi-CMOS）驱动器
公开(公告)号：US5532616A
公开(公告)日：1996-07-02
申请号：US283436
申请日：1994-08-01
申请人： Stanley C. Keeney
发明人： Stanley C. Keeney
IPC分类号： G05F3/26 , H03K19/0175 , H03K17/16
CPC分类号： G05F3/267 , H03K19/017563
摘要： A terminated driver circuit 10 having a controlled output impedance includes an external impedance 12 connected to a bias generator circuit 20 which is operable to generate a plurality of bias voltages in response to a reference current generated by bias generator circuit 20 wherein the reference current magnitude is a function of external impedance 12. An output driver circuit 30 is connected to bias generator circuit 20. Output driver circuit 30 has a plurality of output devices connected to a transmission line and is operable to receive the plurality of bias voltages from bias generator circuit 20 and multiplex them such that only a single bias voltage is driving a single output device at a time. The plurality of bias voltages causes the plurality of output devices to have specific, controlled impedances when conducting wherein the controlled output impedances match the characteristic impedance of a transmission line 40 being driven by terminated driver circuit 10 thereby reducing waveform reflections.
摘要翻译：具有受控输出阻抗的端接驱动器电路10包括连接到偏置发生器电路20的外部阻抗12，该偏置发生器电路20可操作以响应于偏置发生器电路20产生的参考电流而产生多个偏置电压，其中参考电流幅度为输出驱动器电路30连接到偏置发生器电路20.输出驱动器电路30具有连接到传输线的多个输出装置，并且可操作以从偏置发生器电路20接收多个偏置电压并且将它们进行复用，使得一次只有单个偏置电压驱动单个输出设备。多个偏置电压使得多个输出装置在导通时具有特定的受控阻抗，其中受控输出阻抗与由端接的驱动器电路10驱动的传输线40的特性阻抗匹配，从而减少波形反射。

7. 发明授权

US4612499A Test input demultiplexing circuit 失效
标题翻译：测试输入解复用电路
公开(公告)号：US4612499A
公开(公告)日：1986-09-16
申请号：US549121
申请日：1983-11-07
申请人： Bernhard H. Andresen , Stanley C. Keeney
发明人： Bernhard H. Andresen , Stanley C. Keeney
IPC分类号： G01R31/28 , G01R19/165 , G01R31/317 , G01R31/3185
CPC分类号： G01R31/31701
摘要： A test signal, used to initialize an integrated circuit chip for testing, is multiplexed with a data input line of the chip. The test signal circuitry is inactivated during normal operation of the chip. The test circuitry is activated only when a special input signal, which is a voltage at some midpoint between logic states, is applied to the data input.
摘要翻译：用于初始化用于测试的集成电路芯片的测试信号与芯片的数据输入线路复用。测试信号电路在芯片的正常操作期间失活。仅当将特殊输入信号（即逻辑状态之间的某个中点处的电压）施加到数据输入时才会激活测试电路。

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