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    • 1. 发明授权
    • Gate driving scheme for depletion mode devices in buck converters
    • 降压转换器中耗尽型器件的栅极驱动方案
    • US07839131B2
    • 2010-11-23
    • US12163100
    • 2008-06-27
    • Bo YangJason ZhangMichael A. Briere
    • Bo YangJason ZhangMichael A. Briere
    • G05F1/40
    • H02M3/1588H02J7/0018H02J7/345Y02B40/90Y02B70/1466Y10T307/747
    • A circuit comprising a gate driver including first and second switching stages for driving respective sync and control switches, at least one of which is a normally ON depletion mode device, and another circuit connected to the first and second switching stages and including first and second circuits. The first circuit is coupled to the first switching stage and to the sync switch, the first switching stage having a first state wherein the sync switch is on, and a second state wherein a first bias voltage is switched to the gate of the sync switch to turn it off. The second circuit has a first state wherein the control switch is on when the sync switch is off, and a second state wherein the control switch is switched off when the sync switch is on by switching a second bias voltage to the gate of the control switch.
    • 一种包括栅极驱动器的电路,包括用于驱动相应的同步和控制开关的第一和第二开关级,其中至少一个是正常耗尽型器件,以及连接到第一和第二开关级的另一个电路,包括第一和第二电路 。 第一电路耦合到第一开关级和同步开关,第一开关级具有第一状态,其中同步开关导通,以及第二状态,其中第一偏置电压切换到同步开关的栅极至 把它关掉。 第二电路具有第一状态,其中当同步开关断开时控制开关接通;以及第二状态,其中当同步开关接通时,通过将第二偏置电压切换到控制开关的门,控制开关断开 。
    • 2. 发明申请
    • GATE DRIVING SCHEME FOR DEPLETION MODE DEVICES IN BUCK CONVERTERS
    • 闸阀转换器中的取消模式装置的闸门驱动方案
    • US20090051225A1
    • 2009-02-26
    • US12163100
    • 2008-06-27
    • Bo YangJason ZhangMichael A. Briere
    • Bo YangJason ZhangMichael A. Briere
    • H01H47/00
    • H02M3/1588H02J7/0018H02J7/345Y02B40/90Y02B70/1466Y10T307/747
    • A circuit for driving a switching stage including control and sync switches series connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate driver including first and second switching stages for generating gate drive signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch and a circuit connected to the first and second switching stages, the circuit including a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch, a first bias voltage from the first voltage source being switched by the first switching stage, the first switching stage having a first state wherein the sync switch is on, and a second state wherein the first bias voltage is switched to the gate of the sync switch to turn the sync switch off and a second circuit including a first energy storage device for charging with a second bias voltage, the second switching circuit having a first state, wherein the control switch is on when the sync switch is off and having a second state wherein the control switch is switched off when the sync switch is on by switching the second bias voltage to the gate of the control switch.
    • 一种用于驱动开关级的电路,包括连接在开关节点处的控制和同步开关串联,所述控制和同步开关中的至少一个是正常的导通耗尽型装置,所述电路包括栅极驱动器,所述栅极驱动器包括第一和第二开关级,用于产生 分别具有用于同步和控制开关的栅极驱动信号,第一开关级具有第一驱动器输出节点,第二开关级具有第二驱动器输出节点,来自驱动同步开关的第一节点的信号和来自第二驱动器输出节点的信号 节点驱动控制开关和连接到第一和第二开关级的电路,该电路包括提供第一电压源的第一电路,第一电路耦合到第一开关级和同步开关,第一偏置电压来自 第一电压源由第一开关级切换,第一开关级具有第一状态,其中同步开关为o n和第二状态,其中第一偏置电压切换到同步开关的栅极以使同步开关断开,第二电路包括第二电路,第二电路包括用于以第二偏置电压充电的第一能量存储装置,第二开关电路具有 第一状态,其中当同步开关关闭时,控制开关接通,并且具有第二状态,其中当同步开关接通时,通过将第二偏置电压切换到控制开关的门,控制开关被切断。
    • 3. 发明授权
    • DC/DC converter with depletion-mode III-nitride switches
    • 具有耗尽型III族氮化物开关的DC / DC转换器
    • US08674670B2
    • 2014-03-18
    • US12928102
    • 2010-12-03
    • Michael A. BriereJason ZhangBo Yang
    • Michael A. BriereJason ZhangBo Yang
    • H02M3/158
    • H02H7/1213H02M1/32H02M3/1588Y02B70/1466Y02B70/1483
    • Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.
    • 公开了一种降压转换器,用于将降压转换器的输入处的高电压转换为降压转换器的输出处的低电压。 降压转换器包括配置成控制控制开关的占空比的控制电路,控制开关插入降压转换器的输入和输出之间。 同步开关插在输出和地之间。 控制开关和同步开关包括耗尽型III族氮化物晶体管。 在一个实施例中,控制开关和同步开关中的至少一个包括耗尽型GaN HEMT。 降压转换器还包括保护电路,其被配置为在控制电路未上电时禁止通过控制开关的电流传导。
    • 4. 发明申请
    • DC/DC converter with depletion-mode III-nitride switches
    • 具有耗尽型III族氮化物开关的DC / DC转换器
    • US20110080156A1
    • 2011-04-07
    • US12928102
    • 2010-12-03
    • Michael A. BriereJason ZhangBo Yang
    • Michael A. BriereJason ZhangBo Yang
    • H02M3/155
    • H02H7/1213H02M1/32H02M3/1588Y02B70/1466Y02B70/1483
    • Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.
    • 公开了一种降压转换器,用于将降压转换器的输入处的高电压转换为降压转换器的输出处的低电压。 降压转换器包括配置成控制控制开关的占空比的控制电路,控制开关插入降压转换器的输入和输出之间。 同步开关插在输出和地之间。 控制开关和同步开关包括耗尽型III族氮化物晶体管。 在一个实施例中,控制开关和同步开关中的至少一个包括耗尽型GaN HEMT。 降压转换器还包括保护电路,其被配置为在控制电路未上电时禁止通过控制开关的电流传导。
    • 5. 发明授权
    • Gate driver in buck converters
    • 降压转换器中的栅极驱动器
    • US08072202B2
    • 2011-12-06
    • US12925199
    • 2010-10-15
    • Bo YangJason ZhangMichael A. Briere
    • Bo YangJason ZhangMichael A. Briere
    • G05F1/40
    • H02M3/1588H02J7/0018H02J7/345Y02B40/90Y02B70/1466Y10T307/747
    • A circuit comprising a gate driver including first and second switching stages for driving respective sync and control switches, at least one of which is a normally ON depletion mode device, and another circuit connected to the first and second switching stages and including first and second circuits. The first circuit is coupled to the first switching stage and to the sync switch, the first switching stage having a first state wherein the sync switch is on, and a second state wherein a first bias voltage is switched to the gate of the sync switch to turn it off. The second circuit has a first state wherein the control switch is on when the sync switch is off, and a second state wherein the control switch is switched off when the sync switch is on by switching a second bias voltage to the gate of the control switch.
    • 一种包括栅极驱动器的电路,包括用于驱动相应的同步和控制开关的第一和第二开关级,其中至少一个是正常耗尽型器件,以及连接到第一和第二开关级的另一个电路,包括第一和第二电路 。 第一电路耦合到第一开关级和同步开关,第一开关级具有第一状态,其中同步开关导通,以及第二状态,其中第一偏置电压切换到同步开关的栅极至 把它关掉。 第二电路具有第一状态,其中当同步开关断开时控制开关接通;以及第二状态,其中当同步开关接通时,通过将第二偏置电压切换到控制开关的门,控制开关断开 。
    • 7. 发明申请
    • Gate Driver in Buck Converters
    • 降压转换器中的栅极驱动器
    • US20110074375A1
    • 2011-03-31
    • US12925199
    • 2010-10-15
    • Bo YangJason ZhangMichael A. Briere
    • Bo YangJason ZhangMichael A. Briere
    • G05F1/618
    • H02M3/1588H02J7/0018H02J7/345Y02B40/90Y02B70/1466Y10T307/747
    • A circuit for driving a switching stage including control and sync switches series connected at a switching node, at least one of the control and sync switches being a normal ON depletion mode device, the circuit comprising a gate driver including first and second switching stages for generating gate drive signals for the sync and control switches, respectively, the first switching stage having a first driver output node and the second switching stage having a second driver output node, a signal from the first node driving the sync switch and a signal from the second node driving the control switch and a circuit connected to the first and second switching stages, the circuit including a first circuit providing a first voltage source, the first circuit being coupled to the first switching stage and to the sync switch, a first bias voltage from the first voltage source being switched by the first switching stage, the first switching stage having a first state wherein the sync switch is on, and a second state wherein the first bias voltage is switched to the gate of the sync switch to turn the sync switch off and a second circuit including a first energy storage device for charging with a second bias voltage, the second switching circuit having a first state, wherein the control switch is on when the sync switch is off and having a second state wherein the control switch is switched off when the sync switch is on by switching the second bias voltage to the gate of the control switch.
    • 一种用于驱动开关级的电路,包括连接在开关节点处的控制和同步开关串联,所述控制和同步开关中的至少一个是正常的导通耗尽型装置,所述电路包括栅极驱动器,所述栅极驱动器包括第一和第二开关级,用于产生 分别具有用于同步和控制开关的栅极驱动信号,第一开关级具有第一驱动器输出节点,第二开关级具有第二驱动器输出节点,来自驱动同步开关的第一节点的信号和来自第二驱动器输出节点的信号 节点驱动控制开关和连接到第一和第二开关级的电路,该电路包括提供第一电压源的第一电路,第一电路耦合到第一开关级和同步开关,第一偏置电压来自 第一电压源由第一开关级切换,第一开关级具有第一状态,其中同步开关为o n和第二状态,其中第一偏置电压切换到同步开关的栅极以使同步开关断开,第二电路包括第二电路,第二电路包括用于以第二偏置电压充电的第一能量存储装置,第二开关电路具有 第一状态,其中当同步开关关闭时,控制开关接通,并且具有第二状态,其中当同步开关接通时,通过将第二偏置电压切换到控制开关的门,控制开关被切断。
    • 9. 发明授权
    • Synchronous rectifier circuits and method for utilizing common source inductance of the synchronous FET
    • 同步整流电路和方法,用于同步FET的共源电感
    • US07492138B2
    • 2009-02-17
    • US11096929
    • 2005-04-01
    • Jason ZhangBo Yang
    • Jason ZhangBo Yang
    • G05F1/00H02M3/335
    • H02M3/33592H02M3/1588Y02B70/1466Y02B70/1475
    • A method of improving the operation of a synchronous rectifier circuit which includes a switching transistor and synchronous transistor, by providing an operatively effective value of inductance in the current path of the synchronous transistor; which is shared by the control terminal circuit path of the transistor and by selecting a synchronous transistor having a low resistance to a control signal provided at the control terminal, as well as improved synchronous rectifier circuits designed according to the method. When the transistors are MOSFETs, the inductance provided is preferably a purely parasitic common source inductance in the range of about 2 nH to about 3 nH. The synchronous transistor exhibits a low value of gate resistance to facilitate fast energy exchange between the common source inductance and the gate-source capacitance.
    • 一种通过在同步晶体管的电流路径中提供可操作有效的电感值来改善包括开关晶体管和同步晶体管的同步整流电路的操作的方法; 其由晶体管的控制端子电路路径共享,并且通过选择对控制端子处提供的控制信号具有低电阻的同步晶体管以及根据该方法设计的改进的同步整流器电路。 当晶体管是MOSFET时,所提供的电感优选为大约2nH至大约3nH范围内的纯寄生共源电感。 同步晶体管表现出低的栅极电阻值,以促进共源极电感和栅源电容之间的快速能量交换。
    • 10. 发明申请
    • Synchronous rectifier circuits and method for utilizing common source inductance of the synchronous fet
    • 同步整流电路和同步电机的共源电感的方法
    • US20050265057A1
    • 2005-12-01
    • US11096929
    • 2005-04-01
    • Jason ZhangBo Yang
    • Jason ZhangBo Yang
    • H02M3/155H02M3/158H02M3/28H02M3/335H02M7/217
    • H02M3/33592H02M3/1588Y02B70/1466Y02B70/1475
    • A method of improving the operation of a synchronous rectifier circuit which includes a switching transistor and synchronous transistor, by providing an operatively effective value of inductance in the current path of the synchronous transistor; which is shared by the control terminal circuit path of the transistor and by selecting a synchronous transistor having a low resistance to a control signal provided at the control terminal, as well as improved synchronous rectifier circuits designed according to the method. When the transistors are MOSFETs, the inductance provided is preferably a purely parasitic common source inductance in the range of about 2 nH to about 3 nH. The synchronous transistor exhibits a low value of gate resistance to facilitate fast energy exchange between the common source inductance and the gate-source capacitance.
    • 一种通过在同步晶体管的电流路径中提供可操作有效的电感值来改善包括开关晶体管和同步晶体管的同步整流电路的操作的方法; 其由晶体管的控制端子电路路径共享,并且通过选择对控制端子处提供的控制信号具有低电阻的同步晶体管以及根据该方法设计的改进的同步整流器电路。 当晶体管是MOSFET时,所提供的电感优选为大约2nH至大约3nH范围内的纯寄生共源电感。 同步晶体管表现出低的栅极电阻值,以促进共源极电感和栅源电容之间的快速能量交换。